fdt.rar_FDT_V2

/* * Copyright (C) 2011 Samsung Electronics Co.Ltd * Authors: * Seung-Woo Kim <sw0312.kim@samsung.com> * Inki Dae <inki.dae@samsung.com> * Joonyoung Shim <jy0922.shim@samsung.com> * * Based on drivers/media/video/s5p-tv/mixer_reg.c * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * */ #include <drm/drmP.h> #include "regs-mixer.h" #include "regs-vp.h" #include <linux/kernel.h> #include <linux/spinlock.h> #include <linux/wait.h> #include <linux/i2c.h> #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/delay.h> #include <linux/pm_runtime.h> #include <linux/clk.h> #include <linux/regulator/consumer.h> #include <linux/of.h> #include <drm/exynos_drm.h> #include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" #include "exynos_drm_hdmi.h" #include "exynos_drm_iommu.h" #define get_mixer_context(dev) platform_get_drvdata(to_platform_device(dev)) struct hdmi_win_data { dma_addr_t dma_addr; dma_addr_t chroma_dma_addr; uint32_t pixel_format; unsigned int bpp; unsigned int crtc_x; unsigned int crtc_y; unsigned int crtc_width; unsigned int crtc_height; unsigned int fb_x; unsigned int fb_y; unsigned int fb_width; unsigned int fb_height; unsigned int src_width; unsigned int src_height; unsigned int mode_width; unsigned int mode_height; unsigned int scan_flags; bool enabled; bool resume; }; struct mixer_resources { int irq; void __iomem *mixer_regs; void __iomem *vp_regs; spinlock_t reg_slock; struct clk *mixer; struct clk *vp; struct clk *sclk_mixer; struct clk *sclk_hdmi; struct clk *sclk_dac; }; enum mixer_version_id { MXR_VER_0_0_0_16, MXR_VER_16_0_33_0, MXR_VER_128_0_0_184, }; struct mixer_context { struct device *dev; struct drm_device *drm_dev; int pipe; bool interlace; bool powered; bool vp_enabled; u32 int_en; struct mutex mixer_mutex; struct mixer_resources mixer_res; struct hdmi_win_data win_data[MIXER_WIN_NR]; enum mixer_version_id mxr_ver; void *parent_ctx; wait_queue_head_t wait_vsync_queue; atomic_t wait_vsync_event; }; struct mixer_drv_data { enum mixer_version_id version; bool is_vp_enabled; }; static const u8 filter_y_horiz_tap8[] = { 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 0, 0, 0, 2, 4, 5, 6, 6, 6, 6, 6, 5, 5, 4, 3, 2, 1, 1, 0, -6, -12, -16, -18, -20, -21, -20, -20, -18, -16, -13, -10, -8, -5, -2, 127, 126, 125, 121, 114, 107, 99, 89, 79, 68, 57, 46, 35, 25, 16, 8, }; static const u8 filter_y_vert_tap4[] = { 0, -3, -6, -8, -8, -8, -8, -7, -6, -5, -4, -3, -2, -1, -1, 0, 127, 126, 124, 118, 111, 102, 92, 81, 70, 59, 48, 37, 27, 19, 11, 5, 0, 5, 11, 19, 27, 37, 48, 59, 70, 81, 92, 102, 111, 118, 124, 126, 0, 0, -1, -1, -2, -3, -4, -5, -6, -7, -8, -8, -8, -8, -6, -3, }; static const u8 filter_cr_horiz_tap4[] = { 0, -3, -6, -8, -8, -8, -8, -7, -6, -5, -4, -3, -2, -1, -1, 0, 127, 126, 124, 118, 111, 102, 92, 81, 70, 59, 48, 37, 27, 19, 11, 5, }; static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id) { return readl(res->vp_regs + reg_id); } static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id, u32 val) { writel(val, res->vp_regs + reg_id); } static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id, u32 val, u32 mask) { u32 old = vp_reg_read(res, reg_id); val = (val & mask) | (old & ~mask); writel(val, res->vp_regs + reg_id); } static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id) { return readl(res->mixer_regs + reg_id); } static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id, u32 val) { writel(val, res->mixer_regs + reg_id); } static inline void mixer_reg_writemask(struct mixer_resources *res, u32 reg_id, u32 val, u32 mask) { u32 old = mixer_reg_read(res, reg_id); val = (val & mask) | (old & ~mask); writel(val, res->mixer_regs + reg_id); } static void mixer_regs_dump(struct mixer_context *ctx) { #define DUMPREG(reg_id) \ do { \ DRM_DEBUG_KMS(#reg_id " = %08x\n", \ (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \ } while (0) DUMPREG(MXR_STATUS); DUMPREG(MXR_CFG); DUMPREG(MXR_INT_EN); DUMPREG(MXR_INT_STATUS); DUMPREG(MXR_LAYER_CFG); DUMPREG(MXR_VIDEO_CFG); DUMPREG(MXR_GRAPHIC0_CFG); DUMPREG(MXR_GRAPHIC0_BASE); DUMPREG(MXR_GRAPHIC0_SPAN); DUMPREG(MXR_GRAPHIC0_WH); DUMPREG(MXR_GRAPHIC0_SXY); DUMPREG(MXR_GRAPHIC0_DXY); DUMPREG(MXR_GRAPHIC1_CFG); DUMPREG(MXR_GRAPHIC1_BASE); DUMPREG(MXR_GRAPHIC1_SPAN); DUMPREG(MXR_GRAPHIC1_WH); DUMPREG(MXR_GRAPHIC1_SXY); DUMPREG(MXR_GRAPHIC1_DXY); #undef DUMPREG } static void vp_regs_dump(struct mixer_context *ctx) { #define DUMPREG(reg_id) \ do { \ DRM_DEBUG_KMS(#reg_id " = %08x\n", \ (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \ } while (0) DUMPREG(VP_ENABLE); DUMPREG(VP_SRESET); DUMPREG(VP_SHADOW_UPDATE); DUMPREG(VP_FIELD_ID); DUMPREG(VP_MODE); DUMPREG(VP_IMG_SIZE_Y); DUMPREG(VP_IMG_SIZE_C); DUMPREG(VP_PER_RATE_CTRL); DUMPREG(VP_TOP_Y_PTR); DUMPREG(VP_BOT_Y_PTR); DUMPREG(VP_TOP_C_PTR); DUMPREG(VP_BOT_C_PTR); DUMPREG(VP_ENDIAN_MODE); DUMPREG(VP_SRC_H_POSITION); DUMPREG(VP_SRC_V_POSITION); DUMPREG(VP_SRC_WIDTH); DUMPREG(VP_SRC_HEIGHT); DUMPREG(VP_DST_H_POSITION); DUMPREG(VP_DST_V_POSITION); DUMPREG(VP_DST_WIDTH); DUMPREG(VP_DST_HEIGHT); DUMPREG(VP_H_RATIO); DUMPREG(VP_V_RATIO); #undef DUMPREG } static inline void vp_filter_set(struct mixer_resources *res, int reg_id, const u8 *data, unsigned int size) { /* assure 4-byte align */ BUG_ON(size & 3); for (; size; size -= 4, reg_id += 4, data += 4) { u32 val = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]; vp_reg_write(res, reg_id, val); } } static void vp_default_filter(struct mixer_resources *res) { vp_filter_set(res, VP_POLY8_Y0_LL, filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8)); vp_filter_set(res, VP_POLY4_Y0_LL, filter_y_vert_tap4, sizeof(filter_y_vert_tap4)); vp_filter_set(res, VP_POLY4_C0_LL, filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); } static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable) { struct mixer_resources *res = &ctx->mixer_res; /* block update on vsync */ mixer_reg_writemask(res, MXR_STATUS, enable ? MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE); if (ctx->vp_enabled) vp_reg_write(res, VP_SHADOW_UPDATE, enable ? VP_SHADOW_UPDATE_ENABLE : 0); } static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height) { struct mixer_resources *res = &ctx->mixer_res; u32 val; /* choosing between interlace and progressive mode */ val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRASSIVE); if (ctx->mxr_ver != MXR_VER_128_0_0_184) { /* choosing between proper HD and SD mode */ if (height <= 480) val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; else if (height <= 576) val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; else if (height <= 720) val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; else if (height <= 1080) val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; else val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; } mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); } static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height) { struct mixer_resources *res = &ctx->mixer_res; u32 val; if (height == 480) { val = MXR_CFG_RGB601_0_255; } else if (height == 576) { val = MXR_CFG_RGB601_0_255; } else if (height == 720) { val = MXR_CFG_RGB709_16_235; mixer_reg_write(res, MXR_CM_COEFF_Y, (1 << 30) | (94 << 20) | (314 << 10) | (32 << 0)); mixer_reg_write(res, MXR_CM_COEFF_CB, (972 << 20) | (851 << 10) | (225 << 0)); mixer_reg_write(res, MXR_CM_COEFF_CR, (225 << 20) | (820 << 10) | (1004 <<