pch_uart.rar_The Number_lapis

/* *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. * *This program is free software; you can redistribute it and/or modify *it under the terms of the GNU General Public License as published by *the Free Software Foundation; version 2 of the License. * *This program is distributed in the hope that it will be useful, *but WITHOUT ANY WARRANTY; without even the implied warranty of *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *GNU General Public License for more details. * *You should have received a copy of the GNU General Public License *along with this program; if not, write to the Free Software *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. */ #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) #define SUPPORT_SYSRQ #endif #include <linux/kernel.h> #include <linux/serial_reg.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/console.h> #include <linux/serial_core.h> #include <linux/tty.h> #include <linux/tty_flip.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/dmi.h> #include <linux/nmi.h> #include <linux/delay.h> #include <linux/debugfs.h> #include <linux/dmaengine.h> #include <linux/pch_dma.h> enum { PCH_UART_HANDLED_RX_INT_SHIFT, PCH_UART_HANDLED_TX_INT_SHIFT, PCH_UART_HANDLED_RX_ERR_INT_SHIFT, PCH_UART_HANDLED_RX_TRG_INT_SHIFT, PCH_UART_HANDLED_MS_INT_SHIFT, PCH_UART_HANDLED_LS_INT_SHIFT, }; enum { PCH_UART_8LINE, PCH_UART_2LINE, }; #define PCH_UART_DRIVER_DEVICE "ttyPCH" /* Set the max number of UART port * Intel EG20T PCH: 4 port * LAPIS Semiconductor ML7213 IOH: 3 port * LAPIS Semiconductor ML7223 IOH: 2 port */ #define PCH_UART_NR 4 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) #define PCH_UART_RBR 0x00 #define PCH_UART_THR 0x00 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) #define PCH_UART_IER_ERBFI 0x00000001 #define PCH_UART_IER_ETBEI 0x00000002 #define PCH_UART_IER_ELSI 0x00000004 #define PCH_UART_IER_EDSSI 0x00000008 #define PCH_UART_IIR_IP 0x00000001 #define PCH_UART_IIR_IID 0x00000006 #define PCH_UART_IIR_MSI 0x00000000 #define PCH_UART_IIR_TRI 0x00000002 #define PCH_UART_IIR_RRI 0x00000004 #define PCH_UART_IIR_REI 0x00000006 #define PCH_UART_IIR_TOI 0x00000008 #define PCH_UART_IIR_FIFO256 0x00000020 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 #define PCH_UART_IIR_FE 0x000000C0 #define PCH_UART_FCR_FIFOE 0x00000001 #define PCH_UART_FCR_RFR 0x00000002 #define PCH_UART_FCR_TFR 0x00000004 #define PCH_UART_FCR_DMS 0x00000008 #define PCH_UART_FCR_FIFO256 0x00000020 #define PCH_UART_FCR_RFTL 0x000000C0 #define PCH_UART_FCR_RFTL1 0x00000000 #define PCH_UART_FCR_RFTL64 0x00000040 #define PCH_UART_FCR_RFTL128 0x00000080 #define PCH_UART_FCR_RFTL224 0x000000C0 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 #define PCH_UART_FCR_RFTL_SHIFT 6 #define PCH_UART_LCR_WLS 0x00000003 #define PCH_UART_LCR_STB 0x00000004 #define PCH_UART_LCR_PEN 0x00000008 #define PCH_UART_LCR_EPS 0x00000010 #define PCH_UART_LCR_SP 0x00000020 #define PCH_UART_LCR_SB 0x00000040 #define PCH_UART_LCR_DLAB 0x00000080 #define PCH_UART_LCR_NP 0x00000000 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ PCH_UART_LCR_SP) #define PCH_UART_LCR_5BIT 0x00000000 #define PCH_UART_LCR_6BIT 0x00000001 #define PCH_UART_LCR_7BIT 0x00000002 #define PCH_UART_LCR_8BIT 0x00000003 #define PCH_UART_MCR_DTR 0x00000001 #define PCH_UART_MCR_RTS 0x00000002 #define PCH_UART_MCR_OUT 0x0000000C #define PCH_UART_MCR_LOOP 0x00000010 #define PCH_UART_MCR_AFE 0x00000020 #define PCH_UART_LSR_DR 0x00000001 #define PCH_UART_LSR_ERR (1<<7) #define PCH_UART_MSR_DCTS 0x00000001 #define PCH_UART_MSR_DDSR 0x00000002 #define PCH_UART_MSR_TERI 0x00000004 #define PCH_UART_MSR_DDCD 0x00000008 #define PCH_UART_MSR_CTS 0x00000010 #define PCH_UART_MSR_DSR 0x00000020 #define PCH_UART_MSR_RI 0x00000040 #define PCH_UART_MSR_DCD 0x00000080 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) #define PCH_UART_DLL 0x00 #define PCH_UART_DLM 0x01 #define PCH_UART_BRCSR 0x0E #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) #define PCH_UART_HAL_STB1 0 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ PCH_UART_HAL_CLR_RX_FIFO) #define PCH_UART_HAL_DMA_MODE0 0 #define PCH_UART_HAL_FIFO_DIS 0 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ PCH_UART_FCR_FIFO256) #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) #define PCI_VENDOR_ID_ROHM 0x10DB #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ struct pch_uart_buffer { unsigned char *buf; int size; }; struct eg20t_port { struct uart_port port; int port_type; void