library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fourbit is
port(
a : in bit_VECTOR(3 downto 0);
b : in bit_VECTOR(3 downto 0);
y : out bit_VECTOR(4 downto 0)
);
end fourbit;
--}} End of automatically maintained section
architecture fourbit of fourbit is
component fadf is
port(
a : in bit;
b : in bit;
c : in bit;
s : out bit;
ca : out bit
);
end component;