显示模块 -------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity decled is
port( datain:in unsigned(3 downto 0);
dataout:out std_logic_vector(6 downto 0) );
end decled;
architecture decled_ar of decled is
begin
process(datain)
begin
case datain is
when "0000"=>dataout<="0111111";
when "0001"=>dataout<="0000110";
when "0010"=>dataout<="1011011";
when "0011"=>dataout<="1001111";
when "0100"=>dataout<="1100110";
when "0101"=>dataout<="1101101";
when "0110"=>dataout<="1111101";
when "0111"=>dataout<="0000111";
when "1000"=>dataout<="1111111";
when "1001"=>dataout<="1101111";
when others=>dataout<="0000000";
end case;
end process;
end decled_ar;
--顶层模块 --忽略了同一方向不能同时左拐的情况 ------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity my_traffic is
PORT ( clk,en : IN STD_LOGIC;
lampa,lampb : out STD_LOGIC_VECTOR(3 DOWNTO 0);
lampa-RYGW,lampb-RYGW led_disp1,led_disp2,led_disp3,led_disp4:out STD_LOGIC_VECTOR(6 DOWNTO 0) );
END my_traffic;
ARCHITECTURE my_traffic_a OF my_traffic IS
signal astate,bstate,astate_temp,bstate_temp :std_logic_vector(2 downto 0);
SIGNAL num_a,num_b: unsigned(7 downto 0); -- integer range 0 to 65;
signal num_a_disp,num_b_disp :std_logic_vector(7 downto 0);
signal ctla,ctlb : std_logic;
component decled
port( datain:in unsigned(3 downto 0);
dataout:out std_logic_vector(6 downto 0) );
end component;
BEGIN u3:decled port map (datain=>num_a(7 downto 4),dataout=>led_disp1); u4:decled port map (datain=>num_a(3 downto 0),dataout=>led_disp2); u5:decled port map (datain=>num_b(7 downto 4),dataout=>led_disp3); u6:decled port map (datain=>num_b(3 downto 0),dataout=>led_disp4); process(clk,astate_temp,bstate_temp) begin if rising_edge(clk) then astate<=astate_temp; bstate<=bstate_temp; end if; end process; a_ctl : process(clk,num_a,astate) begin if rising_edge(clk) then if en='1' then if ctla='1' then ctla<='0'; case astate is when "000" => num_a<="01010100";lampa<="1000";--RYGW astate_temp<="001"; when "001"=>num_a<="00000100";lampa<="0100"; astate_temp<="010"; when "010" => num_a<="00111001";lampa<="0010"; astate_temp<="011"; when "011"=>num_a<="00000100";lampa<="0100"; astate_temp<="100"; when "100" => num_a<="00010100";lampa<="0001"; astate_temp<="101"; when "101" => num_a<="00000100";lampa<="0100"; astate_temp<="000"; when others => null; end case; elsif ctla='0' then if num_a=0 then ctla<='1'; else if num_a(3 downto 0)=0 then num_a(7 downto 4)<=num_a(7 downto 4)-1; num_a(3 downto 0)<="1001"; else num_a(3 downto 0)<=num_a(3 downto 0)-1; end if; end if; end if; else ctla<='1';astate_temp<="000"; end if; end if; end process a_ctl; b_ctl : process (clk,num_b,bstate) begin if rising_edge(clk) then if en='1' then if ctlb='1' then ctlb<='0'; case bstate is when "000" => num_b<="00000100";lampb<="0100";--RYGW bstate_temp<="001"; when "001" => num_b<="00101001";lampb<="0010"; bstate_temp<="010"; when "010" => num_b<="00000100";lampb<="0100"; bstate_temp<="011"; when "011"=> num_b<="00010100"; lampb<="0001"; bstate_temp<="100"; when "100"=> num_b<="00000100";lampb<="0100"; bstate_temp<="101"; when "101"=> num_b<="01100100";lampb<="1000"; bstate_temp<="000"; when others =>null; end case; elsif ctlb='0' then if num_b= 0 then ctlb<='1'; else if num_b(3 downto 0)=0 then num_b(7 downto 4)<=num_b(7 downto 4)-1; num_b(3 downto 0)<="1001"; else num_b(3 downto 0)<=num_b(3 downto 0)-1; end if; end if; end if; else ctlb<='1'; bstate_temp<="000"; end if; end if; end process b_ctl; END my_traffic_a;
交通灯 EDA程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY JSQ IS
PORT(CLK,RESET,MIN,HOUR,LOAD: IN STD_LOGIC;
DATA3,DATA2,DATA1,DATA0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
MD:IN STD_LOGIC;
RING: OUT STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED_SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY JSQ;
ARCHITECTURE BEH OF JSQ IS
SIGNAL CLK1,CLK2:STD_LOGIC;
SIGNAL A:STD_LOGIC;
signal C: integer range 0 to 999;
SIGNAL S1,S0,SH,SL:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL M1,M0,MH1,ML1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL H1,H0,HH1,HL1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SEL:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL Q_TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL RING3:STD_LOGIC;
begin
p1:process (clk) ——2分频
begin
if(rising_edge(clk)) then
A<= NOT A;
END IF;
CLK1<=A;
end process p1;
p2:process (CLK) ——1千分频
begin
if(rising_edge(clk)) then
if C=999 then C<=0; CLK2<='1';
else C<=C+1; CLK2<='0';
end if;
end if;
end process p2;
P3:PROCESS(CLK) ——八进制加
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF SEL="111" THEN SEL<="000";
ELSE SEL<=SEL+1;
END IF;
END IF;
LED_SEL<=SEL;
END PROCESS P3;
P4:PROCESS(CLK2) ——60秒计数
BEGIN
IF RESET='1' THEN SH<="0000";SL<="0000";
ELSIF(RISING_EDGE(CLK2)) THEN
IF SL="1001" THEN SL<="0000";
IF SH="0101" THEN SH<="0000";
ELSE SH<=SH+1;
END IF;
ELSE SL<=SL+1;
END IF;
END IF;
S1<=SH;
S0<=SL;
END PROCESS P4;
P5:PROCESS(CLK2,S1,S0,RESET,MIN) ——60分计数/校时
BEGIN
IF RESET='1' THEN MH1<="0000";ML1<="0000";
ELSE
IF(RISING_EDGE(CLK2) ) THEN
IF MIN='0' THEN
IF ( S1="0101" AND S0="1001") THEN
IF ML1="1001" THEN ML1<="0000";
IF MH1="0101" THEN MH1<="0000";
ELSE MH1<=MH1+1;
END IF;
ELSE ML1<=ML1+1;
END IF;
END IF;
ELSIF MIN='1' THEN
IF ML1="1001" THEN ML1<="0000";
IF MH1="0101" THEN MH1<="0000";
ELSE MH1<=MH1+1;
END IF;
ELSE ML1<=ML1+1;
END IF;
END IF;
END IF;
M1<=MH1;
M0<=ML1;
END IF;
END PROCESS P5;
P6:PROCESS(CLK2,M1,M0,S1,S0,HOUR,RESET)——24时计数/校时
BEGIN
IF RESET='1' THEN HH1<="0000";HL1<="0000";
ELSIF(RISING_EDGE(CLK2) ) THEN
IF HOUR='0' THEN
IF (M1="0101" AND M0="1001"AND S1="0101" AND S0="1001") THEN
IF HH1<"0010" THEN
IF HL1<"1001" THEN HL1<=HL1+1;
ELSE HL1<="0000"; HH1<=HH1+1;
END IF;
ELSIF (HH1="0010" AND HL1="0011") THEN
HH1<="0000";HL1<="0000";
END IF;
END IF;
ELSIF HOUR='1' THEN
IF HH1<"0010" THEN
IF HL1<"1001" THEN HL1<=HL1+1;
ELSE HL1<="0000"; HH1<=HH1+1;
END IF;
ELSIF (HH1="0010" AND HL1="0011") THEN
HH1<="0000";HL1<="0000";
ELSE HL1<=HL1+1;
END IF;
END IF;
END IF;
H1<=HH1;
H0<=HL1;
END PROCESS P6;
P7:PROCESS(CLK) ——整点报时/闹铃
VARIABLE RING1:STD_LOGIC;
VARIABLE RING2:STD_LOGIC;
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(M1="0101" AND M0= "1001" AND S1="0101") THEN
IF (S0="0000"OR S0="0010"OR S0="0100" OR S0="0110" OR S0="1000" ) THEN
RING1:='1'; RING1:=RING1 AND CLK1;
ELSE RING1:='0';
END IF;
END IF;
IF(M1="0000"AND M0="0000"AND S1="0000" AND S0="0000") THEN
RING1:='1'; RING1:=RING1 AND CLK;
ELSE RING1:='0';
END IF;
IF(LOAD=
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