zynq_fsbl.zip_fsbl_zedboard_zynq_zynq的MD5计算

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EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000110[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0xfa // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x28 // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. ARM_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000001U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. .. DIVISOR = 0x2 // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. .. CPU_3OR2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U // .. .. .. CPU_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U // .. .. .. CPU_1XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U // .. .. .. CPU_PERI_CLKACT = 0x1 // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000114[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000114[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0x12c // .. .. ==> 0XF8000114[21:12] = 0x0000012CU // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U // .. .. EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x20 // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. DDR_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000002U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), // .. .