zhuangtai.rar_报文资源-CSDN文库

共23个文件

xmsgs：2个

v：2个

html：2个

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143 浏览量 2022-09-14 22:50:38 上传评论 1 收藏 49KB RAR 举报

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zhuangtai.rar （23个子文件）

zhuangtai

baowen

xst

projnav.tmp

dump.xst

baowen.prj

work

work.sdbl 16KB

work.sdbx 68B

baowen.v~ 4KB

iseconfig

baowen.projectmgr 5KB

baowen.xreport 20KB

baowen.ngr 25KB

exercise37_text.v 939B

_xmsgs

xst.xmsgs 4KB

pn_parser.xmsgs 779B

baowen.v 7KB

baowen_envsettings.html 9KB

baowen.syr 22KB

baowen.ngc 26KB

baowen_xst.xrpt 14KB

ipcore_dir

baowen_summary.html 5KB

baowen.gise 5KB

baowen.lso 6B

baowen.xise 36KB

webtalk_pn.xml 3KB

baowen.stx 0B

baowen.xst 1KB

baowen.prj 25B

baowen.cmd_log 1KB

<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <center><big><big>System Settings</big></big></center> <A NAME="Environment Settings"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='5'> Environment Settings </TD> </tr> <tr bgcolor='#ffff99'> <td>Environment Variable</td> <td>xst</td> <td>ngdbuild</td> <td>map</td> <td>par</td> </tr> <tr> <td>PATHEXT</td> <td>.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>Path</td> <td>D:\fpga\ise14.7\14.7\ISE_DS\ISE\\lib\nt64; D:\fpga\ise14.7\14.7\ISE_DS\ISE\\bin\nt64; D:\fpga\ise14.7\14.7\ISE_DS\ISE\bin\nt64; D:\fpga\ise14.7\14.7\ISE_DS\ISE\lib\nt64; D:\fpga\ise14.7\14.7\ISE_DS\ISE\..\..\..\DocNav; D:\fpga\ise14.7\14.7\ISE_DS\PlanAhead\bin; D:\fpga\ise14.7\14.7\ISE_DS\EDK\bin\nt64; D:\fpga\ise14.7\14.7\ISE_DS\EDK\lib\nt64; D:\fpga\ise14.7\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin; D:\fpga\ise14.7\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; D:\fpga\ise14.7\14.7\ISE_DS\EDK\gnuwin\bin; D:\fpga\ise14.7\14.7\ISE_DS\EDK\gnu\arm\nt\bin; D:\fpga\ise14.7\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin; D:\fpga\ise14.7\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin; D:\fpga\ise14.7\14.7\ISE_DS\common\bin\nt64; D:\fpga\ise14.7\14.7\ISE_DS\common\lib\nt64; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; D:\matlab\bin; D:\matlab\bin\win64; D:\画板子的软件\System; D:\svn\bin; D:\fpga\modelsim\win64</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX</td> <td>D:\fpga\ise14.7\14.7\ISE_DS\ISE\</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_DSP</td> <td>D:\fpga\ise14.7\14.7\ISE_DS\ISE</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_EDK</td> <td>D:\fpga\ise14.7\14.7\ISE_DS\EDK</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_PLANAHEAD</td> <td>D:\fpga\ise14.7\14.7\ISE_DS\PlanAhead</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> </TABLE> <A NAME="Synthesis Property Settings"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='4'>Synthesis Property Settings </TD> </tr> <tr bgcolor='#ffff99'> <td>Switch Name</td> <td>Property Name</td> <td>Value</td> <td>Default Value</td> </tr> <tr> <td>-ifn</td> <td> </td> <td>baowen.prj</td> <td> </td> </tr> <tr> <td>-ofn</td> <td> </td> <td>baowen</td> <td> </td> </tr> <tr> <td>-ofmt</td> <td> </td> <td>NGC</td> <td>NGC</td> </tr> <tr> <td>-p</td> <td> </td> <td>xc6slx9-2-ftg256</td> <td> </td> </tr> <tr> <td>-top</td> <td> </td> <td>baowen</td> <td> </td> </tr> <tr> <td>-opt_mode</td> <td>Optimization Goal</td> <td>Speed</td> <td>Speed</td> </tr> <tr> <td>-opt_level</td> <td>Optimization Effort</td> <td>1</td> <td>1</td> </tr> <tr> <td>-power</td> <td>Power Reduction</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-iuc</td> <td>Use synthesis Constraints File</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-keep_hierarchy</td> <td>Keep Hierarchy</td> <td>No</td> <td>No</td> </tr> <tr> <td>-netlist_hierarchy</td> <td>Netlist Hierarchy</td> <td>As_Optimized</td> <td>As_Optimized</td> </tr> <tr> <td>-rtlview</td> <td>Generate RTL Schematic</td> <td>Yes</td> <td>No</td> </tr> <tr> <td>-glob_opt</td> <td>Global Optimization Goal</td> <td>AllClockNets</td> <td>AllClockNets</td> </tr> <tr> <td>-read_cores</td> <td>Read Cores</td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-write_timing_constraints</td> <td>Write Timing Constraints</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-cross_clock_analysis</td> <td>Cross Clock Analysis</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-bus_delimiter</td> <td>Bus Delimiter</td> <td><></td> <td><></td> </tr> <tr> <td>-slice_utilization_ratio</td> <td>Slice Utilization Ratio</td> <td>100</td> <td>100</td> </tr> <tr> <td>-bram_utilization_ratio</td> <td>BRAM Utilization Ratio</td> <td>100</td> <td>100</td> </tr> <tr> <td>-dsp_utilization_ratio</td> <td>DSP Utilization Ratio</td> <td>100</td> <td>100</td> </tr> <tr> <td>-reduce_control_sets</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-fsm_extract</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-fsm_encoding</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-safe_implementation</td> <td> </td> <td>No</td> <td>No</td> </tr> <tr> <td>-fsm_style</td> <td> </td> <td>LUT</td> <td>LUT</td> </tr> <tr> <td>-ram_extract</td> <td> </td> <td>Yes</td> <td>Yes</td> </tr> <tr> <td>-ram_style</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-rom_extract</td> <td> </td> <td>Yes</td> <td>Yes</td> </tr> <tr> <td>-shreg_extract</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-rom_style</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-auto_bram_packing</td> <td> </td> <td>NO</td> <td>No</td> </tr> <tr> <td>-resource_sharing</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-async_to_sync</td> <td> </td> <td>NO</td> <td>No</td> </tr> <tr> <td>-use_dsp48</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-iobuf</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-max_fanout</td> <td> </td> <td>100000</td> <td>100000</td> </tr> <tr> <td>-bufg</td> <td> </td> <td>16</td> <td>16</td> </tr> <tr> <td>-register_duplication</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-register_balancing</td> <td> </td> <td>No</td> <td>No</td> </tr> <tr> <td>-optimize_primitives</td> <td> </td> <td>NO</td> <td>No</td> </tr> <tr> <td>-use_clock_enable</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-use_sync_set</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-use_sync_reset</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-iob</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-equivalent_register_removal</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-slice_utilization_ratio_maxmargin</td> <td> </td> <td>5</td> <td>0</td> </tr> </TABLE> <A NAME="Operating System Information"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='5'> Operating System Information </TD> </tr> <tr bgcolor='#ffff99'> <td>Operating System Information</td> <td>xst</td> <td>ngdbuild</td> <td>map</td> <td>

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