/********************************************************************************\
\* DEC6713_USB.c V1.00 *\
\* Copyright 2004 by SEED Electronic Technology LTD. *\
\* All rights reserved. SEED Electronic Technology LTD. *\
\* Restricted rights to use, duplicate or disclose this code are *\
\* granted through contract. *\
\* Designed by: Hongshuai.Li *\
\********************************************************************************/
/********************************************************************************\
\* The example illustrated how C6713 received data from CY7C68001 with interrupt.
You can judge if the operation is right through observing data reveived from PC. *\
\*******************************************************************************/
#include <csl.h>
#include <csl_emif.h>
#include <csl_irq.h>
#include <csl_mcasp.h>
#include <csl_gpio.h>
#include <DEC6713.h>
#include <usb.h>
#include <sx2.h>
#include "codec_iis.h"
#include "descriptors.h"
#define decintreg 0x2
/* global variables */
extern Uint8 IrqValue; /* interrupt register value */
extern Uint8 SetupBuff[8]; /* setup transaction buffer */
extern BOOL sx2Ready; /* status byte for POST */
extern BOOL sx2BusActivity; /* status byte for suspend */
extern BOOL sx2EnumOK; /* status byte for enumeration complete */
extern BOOL sx2EP0Buf; /* status for endpoint 0 buffer */
extern BOOL sx2Setup; /* setup flag set in Int0() ISR */
extern BOOL ReadFlag;
extern BOOL FLAGS_READ; /* FIFO??????*/
//Uint32 ReadReturn;
Uint32 MYMARK;
Uint32 FIFOMARK;
Uint32 counter = 0;
/* global variables specific to this test firmware */
Uint32 FifoWriteCnt ;
Uint16 epdatar[512] ;
Uint16 epdataw[512] ;
Uint16 epdataw1[256];
Uint8 IntStateAdd;
Uint8 StateAdd;
#pragma DATA_SECTION(codecdat,".codec_buffer")
Uint32 codecdat[0x400];
extern far void vectors();
/********************************************************************************/
main()
{
//Uint32 data[4];
MCASP_Handle hMcasp;
GPIO_Handle hGpio;
Uint16 RegValue = 0; /* Temp register value */
Uint16 Sx2int = 0; /* SX2 interrupt register */
Uint16 Usb2or11= 0; /* USB 1.1 mode or 2.0 mode */
Uint16 endpoint0count = 0; /* EP0 counter */
Uint16 endpoint0data[64] ={0};/* EP0 data buffer */
Uint16 i = 0;
// Uint8 audiodata = 0;
Uint16 FifoStatus24 = 0; /* FIFO24 status flag */
Uint16 FifoStatus68 = 0; /* FIFO68 status flag */
Uint16 Fifostatus = 0; /* FIFO status flag */
Uint16 FifoLength = 0; /* Length of FIFO. */
BOOL hshostlink = False; /* True is high speed USB,False is low speed USB */
// BOOL codec_runing = False;
BOOL codec_runing = False;
BOOL codec_halt = False;
// BOOL codec_rev = False;
// BOOL codec_play = False;
// BOOL codec_datok = False;
// BOOL codec_horfull = True;
// BOOL codec_back = False;
// Uint32 codec_count = 0;
// Uint32 codec_sample = 0;
// Uint32 codec_regvalue = 0;
Uint32 audiodata =0;
Uint8 RecievedDataLongth = 0;
Uint8 DataToEndpoint0 = 0; /* Write to Endpoint0 data buffer */
/* Initialize CSL,must when using CSL. */
CSL_init();
/* Initialize DEC6713 board. */
DEC6713_init();
/* Open gpio.13 */
hGpio = GPIO_open(GPIO_DEV0,GPIO_OPEN_RESET);
GPIO_reset(hGpio);
GPIO_pinEnable(hGpio,GPIO_PIN13);
GPIO_pinDirection(hGpio,GPIO_PIN13,GPIO_OUTPUT);
/* Configure interrupt. */
IRQ_setVecs(vectors); /* point to the IRQ vector table */
IRQ_nmiEnable(); /* Enable NMI interrupt */
IRQ_globalEnable(); /* Globally enable interrupts */
/* Map EXTINT6 events to physical interrupt number */
IRQ_map(IRQ_EVT_EXTINT6, 6);
/* Reset the EXTINT6 events. */
IRQ_reset(IRQ_EVT_EXTINT6);
IRQ_RSET(EXTPOL,0x04);
/* Judge if CY7C68001 is ready or not. */
for(;;)
{
Uint8 StateAdd = 0;
Uint32 TempValue = 0;
/* Interrupt or not? */
// CPLD register test.
StateAdd = DEC6713_INTSTAT_REG;
TempValue = DEC6713_cpld_rget(StateAdd);
/*
StateAdd = DEC6713_CTL_REG;
DEC6713_cpld_rset(StateAdd,0x40);
*/
if(!(TempValue&0x10))
{
Sx2int = USB_Command_Read();
if(Sx2int & (SX2_INT_ENUMOK + SX2_INT_READY))
{
/* Open interrupt. */
IRQ_globalDisable();
IRQ_enable(IRQ_EVT_EXTINT6);
IRQ_globalEnable();
break;
}
}
}
/* Enumerate loop. */
while(True)
{
/* Initialize global variables. */
ReadFlag = False; /* false until register read */
sx2Ready = False; /* false until POST or wakeup */
sx2BusActivity = False; /* false until absence or resumption of USB bus activity */
sx2EnumOK = False; /* false until ENUMOK interrupt */
sx2EP0Buf = False; /* false until EP0BUF interrupt */
sx2Setup = False; /* false until SETUP interrupt */
MYMARK = 0;
FIFOMARK = 0;
/* Initialize local variables */
/* Reusable variable for read register data */
RegValue = 0;
/* Load descriptor tables; halt if load fails */
if(!Load_Descriptors(DESCTBL_LEN, &desctbl[0]))
{
while(True);
}
/* After load descriptors, wait for successing Enumerate. */
while( !MYMARK )
{
MYMARK = sx2EnumOK;
}
/* Set interface. */
Write_SX2reg(SX2_IFCONFIG,0xE8);
/* Set POLAR register. SLOE,SLRD and SLWR only are set from EEPROM. */
Write_SX2reg(SX2_FIFOPOLAR, SX2_WUPOL | SX2_EF | SX2_FF);
/* Read the status that CY7C68001 work at full speed or full speed. */
Read_SX2reg(SX2_FNADDR,&Usb2or11);
hshostlink = (Usb2or11 & SX2_HSGRANT) ? True : False;
//hshostlink = False;
/* Initialize USB status. */
if(hshostlink ==True)
{
/* Work at high speed, set interface as 16bits,data package as 512 bytes. */
FifoLength = 0x100;
Write_SX2reg(SX2_EP2PKTLENH , SX2_WORDWIDE | 0x02);
Write_SX2reg(SX2_EP2PKTLENL , 0x00);
Write_SX2reg(SX2_EP4PKTLENH , SX2_WORDWIDE | 0x02);
Write_SX2reg(SX2_EP4PKTLENL , 0x00);
Write_SX2reg(SX2_EP6PKTLENH , SX2_WORDWIDE | 0x02);
Write_SX2reg(SX2_EP6PKTLENL , 0x00);
Write_SX2reg(SX2_EP8PKTLENH , SX2_WORDWIDE | 0x02);
Write_SX2reg(SX2_EP8PKTLENL , 0x00);
}
else
{
/* Work at full speed, set interface as 16bits,data package as 64bytes. */
FifoLength =0x20;
Write_SX2reg(SX2_EP2PKTLENH , SX2_WORDWIDE);
Write_SX2reg(SX2_EP2PKTLENL , 0x40);
Write_SX2reg(SX2_EP4PKTLENH , SX2_WORDWIDE);
Write_SX2reg(SX2_EP4PKTLENL , 0x40);
Write_SX2reg(SX2_EP6PKTLENH , SX2_WORDWIDE);
Write_SX2reg(SX2_EP6PKTLENL , 0x40);
Write_SX2reg(SX2_EP8PKTLENH , SX2_WORDWIDE);
Write_SX2reg(SX2_EP8PKTLENL , 0x40);
}
/* Set FLAGA as the flag for EP6 empty. */
/* Set FLAGB as the flag for EP8 empty. */
/* FLAGC and FLAGD default. */
Write_SX2reg(SX2_FLAGAB, SX2_FLAGA_FF6 | SX2_FLAGB_FF8);
/* Clear all endpoints. */
Write_SX2reg(SX2_INPKTEND, SX2_CLEARALL);
Read_SX2reg(SX2_EP68FLAGS, &FifoStatus68);
/* After enumerate process, loop main program. */
while(sx2EnumOK)
{
/* CODEC CIRCLE running */
if(codec_runing == True)
{
if(codec_halt == True)
{
codec_runing = False;
codec_halt = False;
}
else
{
if (MCASP_RGETH(hMcasp, SRCTL6) & 0x20)
{
audiodata = MCASP_read32Cfg(hMcasp,MCASP_RBUF6);
}
if (MCASP_RGETH(hMcasp, SRCTL7) & 0x10)
{
MCASP_write32Cfg(hMcasp,MCASP_XBUF7,audiodata);
}
}
} // CODEC circle
/* Read FIFO status. */
if(FLAGS_READ)
{
FLAGS_READ = False;
//Write_SX2reg(SX2_INPKTEND, SX2_CLEARALL);
/* FIFO24 read */
if(Read_SX2reg(SX2_EP24FLAGS, &FifoSta
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