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<!@TC:1188890533>
#Build: Synplify Pro 8.6.2H, Build 017R, Dec 7 2006
#install: D:\Libero\Synplify\Synplify_862H
#OS: Windows XP 5.1
#Hostname: SHOUJINQIAO
#Tue Sep 04 15:22:06 2007
<a name=compilerReport1>$ Start of Compile
#Tue Sep 04 15:22:06 2007
Synplicity Verilog Compiler, version 3.7, Build 090R, built Nov 17 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
@I::"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v"
@I::"C:\Actelprj\yan\DualPortRAM\hdl\rec.v"
@I::"C:\Actelprj\yan\DualPortRAM\hdl\send.v"
@I::"C:\Actelprj\yan\DualPortRAM\smartgen\RAM2k8\RAM2k8.v"
@I::"C:\Actelprj\yan\DualPortRAM\hdl\writeram.v"
@I::"C:\Actelprj\yan\DualPortRAM\hdl\top.v"
Verilog syntax check successful!
File C:\Actelprj\yan\DualPortRAM\hdl\writeram.v changed - recompiling
Selecting top level module top
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\dualportram\hdl\rec.v:5:7:5:10:@N:CG364:@XP_MSG">rec.v(5)</a><!@TM:1188890533> | Synthesizing module rec
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\rec.v:38:0:38:6:@W:CL170:@XP_MSG">rec.v(38)</a><!@TM:1188890533> | Pruning bit <9> of UartBuff_6[9:0] - not in use ...</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:6:7:6:11:@N:CG364:@XP_MSG">send.v(6)</a><!@TM:1188890533> | Synthesizing module send
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <9> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <8> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <7> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <6> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <5> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <4> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <3> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <2> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL170:@XP_HELP">CL170</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:54:0:54:6:@W:CL170:@XP_MSG">send.v(54)</a><!@TM:1188890533> | Pruning bit <1> of Datainbuf2_6[9:0] - not in use ...</font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:42:0:42:6:@W:CL189:@XP_MSG">send.v(42)</a><!@TM:1188890533> | Register bit Datainbuf[0] is always 0, optimizing ...</font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:42:0:42:6:@W:CL189:@XP_MSG">send.v(42)</a><!@TM:1188890533> | Register bit Datainbuf[9] is always 1, optimizing ...</font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:42:0:42:6:@W:CL171:@XP_MSG">send.v(42)</a><!@TM:1188890533> | Pruning Register bit <9> of Datainbuf[9:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\dualportram\hdl\send.v:42:0:42:6:@W:CL171:@XP_MSG">send.v(42)</a><!@TM:1188890533> | Pruning Register bit <0> of Datainbuf[9:0] </font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\dualportram\hdl\writeram.v:2:7:2:15:@N:CG364:@XP_MSG">writeram.v(2)</a><!@TM:1188890533> | Synthesizing module writeram
@N:<a href="@N:CL177:@XP_HELP">CL177</a> : <a href="c:\actelprj\yan\dualportram\hdl\writeram.v:125:0:125:6:@N:CL177:@XP_MSG">writeram.v(125)</a><!@TM:1188890533> | Sharing sequential element rst1.
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\libero\synplify\synplify_862h\lib\proasic\fusion.v:2043:7:2043:10:@N:CG364:@XP_MSG">fusion.v(2043)</a><!@TM:1188890533> | Synthesizing module VCC
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\libero\synplify\synplify_862h\lib\proasic\fusion.v:1224:7:1224:10:@N:CG364:@XP_MSG">fusion.v(1224)</a><!@TM:1188890533> | Synthesizing module GND
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\libero\synplify\synplify_862h\lib\proasic\fusion.v:2267:8:2267:14:@N:CG364:@XP_MSG">fusion.v(2267)</a><!@TM:1188890533> | Synthesizing module RAM4K9
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\dualportram\smartgen\ram2k8\ram2k8.v:5:7:5:13:@N:CG364:@XP_MSG">ram2k8.v(5)</a><!@TM:1188890533> | Synthesizing module RAM2k8
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\dualportram\hdl\top.v:2:7:2:10:@N:CG364:@XP_MSG">top.v(2)</a><!@TM:1188890533> | Synthesizing module top
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="c:\actelprj\yan\dualportram\hdl\top.v:47:8:47:10:@W:CS148:@XP_MSG">top.v(47)</a><!@TM:1188890533> | Undriven input DINB, tying to 0</font>
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="c:\actelprj\yan\dualportram\hdl\top.v:47:8:47:10:@W:CS148:@XP_MSG">top.v(47)</a><!@TM:1188890533> | Undriven input ADDRB, tying to 0</font>
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="c:\actelprj\yan\dualportram\hdl\top.v:47:8:47:10:@W:CS148:@XP_MSG">top.v(47)</a><!@TM:1188890533> | Undriven input RWB, tying to 0</font>
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="c:\actelprj\yan\dualportram\hdl\top.v:47:8:47:10:@W:CS148:@XP_MSG">top.v(47)</a><!@TM:1188890533> | Undriven input BLKB, tying to 0</font>
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="c:\actelprj\yan\dualportram\hdl\top.v:47:8:47:10:@W:CS148:@XP_MSG">top.v(47)</a><!@TM:1188890533> | Undriven input CLKB, tying to 0</font>
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 04 15:22:06 2007
###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.0, Build 368R, Built Nov 27 2006 12:29:38
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
Product Version Version 8.6.2H
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1188890533> | Running in 32-bit mode.
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1188890533> | Gated clock conversion disabled
<font color=#A52A2A>@W:<a href="@W:BN153:@XP_HELP">BN153</a> : <!@TM:1188890533> | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking</font>
<font color=#A52A2A>@W:<a href="@W:BN153:@XP_HELP">BN153</a> : <!@TM:1188890533> | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking</font>
<font color=#A52A2A>@W:<a href="@W:BN154:@XP_HELP">BN154</a> : <!@TM:1188890533> | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed</font>
Automatic dissolve at startup in view:work.top(ve
dual_RAM.rar （68个子文件） 
dual_RAM Source File 
rec.v 2KB writeram.v 3KB send.v 2KB waveperl.log 0B top.v 1KB Project DualPortRAM coreconsole stimulus hdl rec.v 2KB hdlsynchk.tcl 122B writeram.v 3KB send.v 2KB top.v 1KB constraint component synthesis stdout.log 13KB syntmp top_flink.htm 355B sap.log 1KB top_srr.htm 45KB top.plg 1KB top_toc.htm 2KB top.msg 2KB top.htm 316B top_drc.rpt 10KB top.fse 0B top.srr 40KB top_syn.prj 698B top.tlg 3KB top.areasrr 7KB top.sap 5KB top.sdf 169KB top.srs 30KB top.srm 397KB top_sdc.sdc 310B traplog.tlg 5KB top.map 0B top.srd 141KB .recordref 0B top.edn 285KB smartgen RAM2k8_work.ixf 2KB RAM2k8 RAM2k8_R0C1.mem 6KB RAM2k8_R0C0.mem 6KB RAM2k8.log 3KB RAM2k8.shx 0B RAM2k8_R0C2.mem 6KB RAM2k8.v 7KB RAM2k8.gen 728B RAM2k8_R0C3.mem 6KB RAM2k8.cxf 3KB smartgen.aws 396B designer impl1 designer_genhdl.log 11KB top.tcl 169B top.ide_des 637B top.dtf verify.log 233B top.adb 388KB top.pdb.depends 0B top.pdb 92KB top.stp 74KB top_fp projectData top.pdb 91KB top.log 823B $$FlashPro_FPBBALTLPT1.L$$ 432B top.pro 1KB simulation designer.log 13KB phy_synthesis viewdraw vf project.lst 52B sch sym wir viewdraw.ini 2KB simulation RAM2k8_R0C1.mem 6KB RAM2k8_R0C0.mem 6KB modelsim.ini.sav 217B RAM2k8_R0C2.mem 6KB modelsim.ini 222B RAM2k8_R0C3.mem 6KB meminit.dat 3KB DualPortRAM.prj 7KB资源评论
