SDRAM.rar_6416 cmd_CSL_cmd_dec6416 gel_seed

/***************************************************************************** FILENAME: SDRAM.C DESIGNER: 戴展波 DATE： 2004/09/25 ******************************************************************************/ #include <stdio.h> #include <csl.h> #include <csl_irq.h> #include <csl_chip.h> #include <csl_emifa.h> static EMIFA_Config MyEmifaConfig = { EMIFA_GBLCTL_RMK ( EMIFA_GBLCTL_EK2RATE_FULLCLK, //1 X EMIF input clock EMIFA_GBLCTL_EK2HZ_CLK, //eclkout2 continue output during hold EMIFA_GBLCTL_EK2EN_ENABLE, //eclkout2 enable output EMIFA_GBLCTL_BRMODE_MRSTATUS, //bus request is memory access or refresh pending/in progress EMIFA_GBLCTL_NOHOLD_DISABLE, EMIFA_GBLCTL_EK1HZ_CLK, //eclkout1 continue output during hold EMIFA_GBLCTL_EK1EN_ENABLE, //eclkout1 enable output EMIFA_GBLCTL_CLK4EN_ENABLE, //clkout4 output enable EMIFA_GBLCTL_CLK6EN_ENABLE //clkout6 output enable ), 0xffffffd3, //64BIT SDRAM // 0xffffff33, //32BIT SDRAM // 0xffffff93, //16bit SDRAM // 0xffffff83, //8bit SDRAM 0xffffffe3, 0x22a28a22, 0x22a28a22, EMIFA_SDCTL_RMK ( EMIFA_SDCTL_SDBSZ_4BANKS, //SDRAM bank size 4 banks EMIFA_SDCTL_SDRSZ_11ROW, //row number = 11 EMIFA_SDCTL_SDCSZ_8COL, //column number = 8 EMIFA_SDCTL_RFEN_ENABLE, //SDRAM refresh enable //EMIFA_SDCTL_INIT_NO, //SDRAM 配置完每个CE空间后，不初始化 EMIFA_SDCTL_INIT_YES, //SDRAM 配置完每个CE空间后，初始化 EMIFA_SDCTL_TRCD_OF(2), //TRCD = (Trcd / Tcyc) - 1 EMIFA_SDCTL_TRP_OF(2), //TRP = (Trp / Tcyc) - 1 EMIFA_SDCTL_TRC_OF(8), EMIFA_SDCTL_SLFRFR_DISABLE //self refresh mode disable ), EMIFA_SDTIM_RMK ( EMIFA_SDTIM_XRFR_DEFAULT, //EXT TIMER default EMIFA_SDTIM_PERIOD_OF(2083) //refresh period,clockout1 = 10ns ), EMIFA_SDEXT_RMK ( EMIFA_SDEXT_WR2RD_OF(0), //cycles between write to read command = 1,subtract 1 is 0 EMIFA_SDEXT_WR2DEAC_OF(1), //cycles between write to precharge = 2 EMIFA_SDEXT_WR2WR_OF(1), //cycles between write to write = 2 EMIFA_SDEXT_R2WDQM_OF(1), //cycles between read to bex = 2 EMIFA_SDEXT_RD2WR_OF(0), //cycles between read to write = 1 EMIFA_SDEXT_RD2DEAC_OF(1), // EMIFA_SDEXT_RD2RD_OF(0), // EMIFA_SDEXT_THZP_OF(2), //Troh = 3 cycle EMIFA_SDEXT_TWR_OF(1), //Twr = 1 clock +6 ns EMIFA_SDEXT_TRRD_OF(0), //Trrd = 12ns EMIFA_SDEXT_TRAS_OF(5), //Tras = 42ns EMIFA_SDEXT_TCL_OF(1) //cas latency = 3 clock ), 0x00000002, 0x00000002, 0x00000002, 0x00000002 }; //volatile Uint32* SDRAM_FIRST_ADDRESS = (volatile Uint32 *) 0x80000000; #pragma DATA_SECTION(sdram_data,".off_ram"); unsigned int sdram_data[0x10000]; extern far void vectors(); void main() { int i; Uint32 good_flag; good_flag = 0; //初始化CSL CSL_init(); //配置EMIFA EMIFA_config(&MyEmifaConfig); IRQ_setVecs(vectors); IRQ_nmiEnable(); IRQ_globalEnable(); for(i = 0; i < 0x400000; i++) { sdram_data[i] = 0; } // *SDRAM_FIRST_ADDRESS = 0x12345678; for(i = 0; i < 0x400000; i++) { sdram_data[i] = 0x12345678+i; } for(i = 0; i < 0x400000; i++) { if(sdram_data[i] != 0x12345678+i) { good_flag = 0; break; } good_flag = 1; } if(good_flag == 1) { printf("SDRAM TEST IS OK!"); } else { printf("SDRAM TEST IS FAILED!"); } }