library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_add is
Port ( A0 : in STD_LOGIC_VECTOR(3 DOWNTO 0);
A1 : in STD_LOGIC_VECTOR(3 DOWNTO 0);
B0 : in STD_LOGIC_VECTOR(3 DOWNTO 0);
B1 : in STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CIN : in STD_LOGIC;
Q0 : out STD_LOGIC_VECTOR(3 DOWNTO 0);
Q1 : out STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end bcd_add;
--定义输入输出端口
architecture Behavioral of bcd_add is
SIGNAL QQ0,QQ1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CHOOSE:STD_LOGIC;
begin
PROCESS(CLK,RST)
VARIABLE CIN0,CIN1,COUT1,CIN2:STD_LOGIC_VECTOR(4 DOWNTO 0);
VARIABLE AA0,AA1,BB0,BB1:STD_LOGIC_VECTOR(4 DOWNTO 0);
VARIABLE TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUT0:STD_LOGIC;
BEGIN
IF RST='1' THEN
AA0:="00000";
AA1:="00000";
BB0:="00000";
BB1:="00000";
CIN0:="00000";
CIN1:="00000";
TEMP:="0000";
COUT0:='0';
COUT1:="00000";
QQ0<="0000";
QQ1<="0000";
Q0<="0000";
Q1<="0000";
COUT<="0000";
CHOOSE<='0';
--通过RST进行置位
ELSIF CLK'EVENT AND CLK='1' THEN
IF CHOOSE='1' THEN
AA0:='0'&QQ0;
AA1:='0'&QQ1;
ELSE
AA0:='0'&A0;
AA1:='0'&A1;
END IF;
--判断累加是否为第一次，同时为加数、被加数添加进位扩展
BB0:='0'&B0;
BB1:='0'&B1;
CIN0:='0'&'0'&'0'&'0'&CIN;
CIN1:=AA0+BB0+CIN0;
CHOOSE<='1';
--第一次加法结束后进行累加
IF CIN1<"01010" THEN
QQ0<=CIN1(3 DOWNTO 0);
Q0<=CIN1(3 DOWNTO 0);
COUT0:='0';
ELSE
QQ0<=CIN1(3 DOWNTO 0) + 6;
Q0<=CIN1(3 DOWNTO 0) + 6;
COUT0:='1';
END IF;
--低位加法并进行调整
COUT1:='0'&'0'&'0'&'0'&COUT0;
CIN2:=AA1+BB1+COUT1;
IF CIN2<"01010" THEN
QQ1<=CIN2(3 DOWNTO 0);
Q1<=CIN2(3 DOWNTO 0);
ELSE
QQ1<=CIN2(3 DOWNTO 0)+6;
Q1<=CIN2(3 DOWNTO 0)+6;
--高位加法并进行调整
TEMP:=TEMP+1;
COUT<=TEMP;
--进位累加
END IF;
END IF;
END PROCESS;
end Behavioral;
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