#ifndef _MC68VZ328_H_
#define _MC68VZ328_H_
#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
#define WORD_REF(addr) (*((volatile unsigned short*)addr))
#define LONG_REF(addr) (*((volatile unsigned long*)addr))
#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
/**********
*
* 0xFFFFF0xx -- System Control
*
**********/
/*
* System Control Register (SCR)
*/
#define SCR_ADDR 0xfffff000
#define SCR BYTE_REF(SCR_ADDR)
#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
#define SCR_DMAP 0x04 /* Double Map */
#define SCR_SO 0x08 /* Supervisor Only */
#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
#define SCR_PRV 0x20 /* Privilege Violation */
#define SCR_WPV 0x40 /* Write Protect Violation */
#define SCR_BETO 0x80 /* Bus-Error TimeOut */
/*
* Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
*/
#define MRR_ADDR 0xfffff004
#define MRR LONG_REF(MRR_ADDR)
/**********
*
* 0xFFFFF1xx -- Chip-Select logic
*
**********/
/*
* Chip Select Group Base Registers
*/
#define CSGBA_ADDR 0xfffff100
#define CSGBB_ADDR 0xfffff102
#define CSGBC_ADDR 0xfffff104
#define CSGBD_ADDR 0xfffff106
#define CSGBA WORD_REF(CSGBA_ADDR)
#define CSGBB WORD_REF(CSGBB_ADDR)
#define CSGBC WORD_REF(CSGBC_ADDR)
#define CSGBD WORD_REF(CSGBD_ADDR)
/*
* Chip Select Registers
*/
#define CSA_ADDR 0xfffff110
#define CSB_ADDR 0xfffff112
#define CSC_ADDR 0xfffff114
#define CSD_ADDR 0xfffff116
#define CSA WORD_REF(CSA_ADDR)
#define CSB WORD_REF(CSB_ADDR)
#define CSC WORD_REF(CSC_ADDR)
#define CSD WORD_REF(CSD_ADDR)
#define CSA_EN 0x0001 /* Chip-Select Enable */
#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSA_SIZ_SHIFT 1
#define CSA_WS_MASK 0x0070 /* Wait State */
#define CSA_WS_SHIFT 4
#define CSA_BSW 0x0080 /* Data Bus Width */
#define CSA_FLASH 0x0100 /* FLASH Memory Support */
#define CSA_RO 0x8000 /* Read-Only */
#define CSB_EN 0x0001 /* Chip-Select Enable */
#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSB_SIZ_SHIFT 1
#define CSB_WS_MASK 0x0070 /* Wait State */
#define CSB_WS_SHIFT 4
#define CSB_BSW 0x0080 /* Data Bus Width */
#define CSB_FLASH 0x0100 /* FLASH Memory Support */
#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
#define CSB_UPSIZ_SHIFT 11
#define CSB_ROP 0x2000 /* Readonly if protected */
#define CSB_SOP 0x4000 /* Supervisor only if protected */
#define CSB_RO 0x8000 /* Read-Only */
#define CSC_EN 0x0001 /* Chip-Select Enable */
#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSC_SIZ_SHIFT 1
#define CSC_WS_MASK 0x0070 /* Wait State */
#define CSC_WS_SHIFT 4
#define CSC_BSW 0x0080 /* Data Bus Width */
#define CSC_FLASH 0x0100 /* FLASH Memory Support */
#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
#define CSC_UPSIZ_SHIFT 11
#define CSC_ROP 0x2000 /* Readonly if protected */
#define CSC_SOP 0x4000 /* Supervisor only if protected */
#define CSC_RO 0x8000 /* Read-Only */
#define CSD_EN 0x0001 /* Chip-Select Enable */
#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSD_SIZ_SHIFT 1
#define CSD_WS_MASK 0x0070 /* Wait State */
#define CSD_WS_SHIFT 4
#define CSD_BSW 0x0080 /* Data Bus Width */
#define CSD_FLASH 0x0100 /* FLASH Memory Support */
#define CSD_DRAM 0x0200 /* Dram Selection */
#define CSD_COMB 0x0400 /* Combining */
#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
#define CSD_UPSIZ_SHIFT 11
#define CSD_ROP 0x2000 /* Readonly if protected */
#define CSD_SOP 0x4000 /* Supervisor only if protected */
#define CSD_RO 0x8000 /* Read-Only */
/*
* Emulation Chip-Select Register
*/
#define EMUCS_ADDR 0xfffff118
#define EMUCS WORD_REF(EMUCS_ADDR)
#define EMUCS_WS_MASK 0x0070
#define EMUCS_WS_SHIFT 4
/**********
*
* 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
*
**********/
/*
* PLL Control Register
*/
#define PLLCR_ADDR 0xfffff200
#define PLLCR WORD_REF(PLLCR_ADDR)
#define PLLCR_DISPLL 0x0008 /* Disable PLL */
#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
#define PLLCR_PRESC 0x0020 /* VCO prescaler */
#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
#define PLLCR_SYSCLK_SEL_SHIFT 8
#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
#define PLLCR_LCDCLK_SEL_SHIFT 11
/* '328-compatible definitions */
#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
/*
* PLL Frequency Select Register
*/
#define PLLFSR_ADDR 0xfffff202
#define PLLFSR WORD_REF(PLLFSR_ADDR)
#define PLLFSR_PC_MASK 0x00ff /* P Count */
#define PLLFSR_PC_SHIFT 0
#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
#define PLLFSR_QC_SHIFT 8
#define PLLFSR_PROT 0x4000 /* Protect P & Q */
#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
/*
* Power Control Register
*/
#define PCTRL_ADDR 0xfffff207
#define PCTRL BYTE_REF(PCTRL_ADDR)
#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
#define PCTRL_WIDTH_SHIFT 0
#define PCTRL_PCEN 0x80 /* Power Control Enable */
/**********
*
* 0xFFFFF3xx -- Interrupt Controller
*
**********/
/*
* Interrupt Vector Register
*/
#define IVR_ADDR 0xfffff300
#define IVR BYTE_REF(IVR_ADDR)
#define IVR_VECTOR_MASK 0xF8
/*
* Interrupt control Register
*/
#define ICR_ADDR 0xfffff302
#define ICR WORD_REF(ICR_ADDR)
#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
/*
* Interrupt Mask Register
*/
#define IMR_ADDR 0xfffff304
#define IMR LONG_REF(IMR_ADDR)
/*
* Define the names for bit positions first. This is useful for
* request_irq
*/
#define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */
#define TMR_IRQ_NUM 1 /* Timer 1 interrupt */
#define UART1_IRQ_NUM 2 /* UART 1 interrupt */
#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
#define RTC_IRQ_NUM 4 /* RTC interrupt */
#define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */
#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
#define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
#define INT0_IRQ_NUM 8 /* External INT0 */
#define INT1_IRQ_NUM 9 /* External INT1 */
#define INT2_IRQ_NUM 10 /* External INT2 */
#define INT3_IRQ_NUM 11 /* External INT3 */
#define UART2_IRQ_NUM 12 /* UART 2 interrupt */
#define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
#define IRQ1_IRQ_NUM 16 /* IRQ1 */
#define IRQ2_IRQ_NUM 17 /* IRQ2 */
#define IRQ3_IRQ_NUM 18 /* IRQ3 */
#define IRQ6_IRQ_NUM 19 /* IRQ6 */
#define IRQ5_IRQ_NUM 20 /* IRQ5 */
#define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */
#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
#define SPI_IRQ_NUM SPI2_IRQ_NUM
/* '328-compatible definitions */
#define SPIM_IRQ_NUM SPI_IRQ_NUM
#define TMR1_IRQ_NUM TMR_IRQ_NUM
#define UART_IRQ_NUM UART1_IRQ_NUM
/*
* Here go the bitmasks themselves
*/
#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
#define IMR_MINT2 (1 << INT2_IRQ
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