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语音时钟公历转阴历 (最终)

HEF45_DataSheet.pdf 105KB

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7518822[1].jpg 56KB

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 

  

 

SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 12 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Contain Eight Flip-Flops With Single-Rail

Outputs

D Direct Clear Input

D Individual Data Input to Each Flip-Flop

D Applications Include:

− Buffer/Storage Registers

− Shift Registers

− Pattern Generators

description

CLR

GND

CLK

SN54HC273 ...J OR W PACKAGE

SN74HC273 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

CLR

GND

CLK

SN54HC273 . . . FK PACKAGE

(TOP VIEW)

description/ordering information

These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 20 SN74HC273N SN74HC273N

SOIC − DW

Tube of 25 SN74HC273DW

HC273

SOIC − DW

Reel of 2000 SN74HC273DWR

HC273

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC273NSR HC273

−40°C to 85°C

SSOP − DB Reel of 2000 SN74HC273DBR HC273

Tube of 70 SN74HC273PW

TSSOP − PW

Reel of 2000 SN74HC273PWR

HC273

TSSOP − PW

Reel of 250 SN74HC273PWT

HC273

CDIP − J Tube of 20 SNJ54HC273J SNJ54HC273J

−55°C to 125°C

CFP − W Tube of 85 SNJ54HC273W SNJ54HC273W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC273FK SNJ54HC273FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

  ! " #$%! "  &$'(#! )!%*

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$(%"" !+%-"% !%)*  (( !+% &)$#!" &)$#!

&#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"*

 

  

 

SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related

directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has

no effect at the output.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR CLK D

OUTPUT

L X X L

H ↑ HH

H ↑ LL

H L X Q

logic diagram (positive logic)

CLK

CLR

logic diagram, each flip-flop (positive logic)

CLK(I)

 

  

 

SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0 or V

> V

) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0 or V

> V

) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

= 0 to V

) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC273 SN74HC273

UNIT

MIN NOM MAX MIN NOM MAX

UNIT

Supply voltage 2 5 6 2 5 6 V

= 2 V 1.5 1.5

High-level input voltage

= 4.5 V

3.15 3.15

High-level input voltage

= 6 V 4.2 4.2

= 2 V 0.5 0.5

Low-level input voltage

= 4.5 V

1.35 1.35

Low-level input voltage

= 6 V 1.8 1.8

Input voltage 0 V

0 V

Output voltage 0 V

0 V

= 2 V 1000 1000

∆t/∆v Input transition rise/fall time

= 4.5 V

500 500

∆t/∆v

Input transition rise/fall time

= 6 V 400 400

Operating free-air temperature −55 125 −40 85 °C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report, Implications

of Slow or Floating CMOS Inputs, literature number SCBA004.

 

  

 

SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

= 25°C SN54HC273 SN74HC273

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN MAX MIN MAX

UNIT

2 V 1.9 1.998 1.9 1.9

= −20 µA

4.5 V 4.4 4.499 4.4 4.4

= V

or V

= −20 µA

6 V 5.9 5.999 5.9 5.9

= V

or V

= −4 mA 4.5 V 3.98 4.3 3.7 3.84

= −5.2 mA 6 V 5.48 5.8 5.2 5.34

2 V 0.002 0.1 0.1 0.1

= 20 µA

4.5 V 0.001 0.1 0.1 0.1

= V

or V

= 20 µA

6 V 0.001 0.1 0.1 0.1

= V

or V

= 4 mA 4.5 V 0.17 0.26 0.4 0.33

= 5.2 mA 6 V 0.15 0.26 0.4 0.33

= V

or 0 6 V ±0.1 ±100 ±1000 ±1000 nA

= V

or 0, I

= 0 6 V 8 160 80 µA

2 V to 6 V 3 10 10 10 pF

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

= 25°C SN54HC273 SN74HC273

UNIT

MIN MAX MIN MAX MIN MAX

UNIT

2 V 5 4 4

clock

Clock frequency

4.5 V

27 18 21

MHz

clock

Clock frequency

6 V 32 21 25

MHz

2 V 80 120 100

CLR low

4.5 V 16 24 20

Pulse duration

CLR low

6 V 14 20 17

Pulse duration

2 V 80 120 100

CLK high or low

4.5 V 16 24 20

CLK high or low

6 V 14 20 17

2 V 100 150 125

Data

4.5 V 20 30 25

Setup time before CLK↑

Data

6 V 17 25 21

Setup time before CLK↑

2 V 100 150 125

CLR inactive

4.5 V 20 30 25

CLR inactive

6 V 17 25 21

2 V 0 0 0

Hold time, data after CLK↑

4.5 V

0 0 0

Hold time, data after CLK

6 V 0 0 0

 

  

 

SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, C

= 50 pF (unless

otherwise noted) (see Figure 1)

PARAMETER

FROM

= 25°C SN54HC273 SN74HC273

UNIT

PARAMETER

FROM

(INPUT)

(OUTPUT)

MIN TYP MAX MIN MAX MIN MAX

UNIT

2 V 5 11 4 4

max

4.5 V 27 50 18 21

MHz

max

6 V 32 60 21 25

MHz

2 V 55 160 240 200

PHL

CLR Any

4.5 V 15 32 48 40

PHL

CLR

Any

6 V 12 27 41 34

2 V 56 160 240 200

CLK Any

4.5 V 15 32 48 40

CLK

Any

6 V 13 27 41 34

2 V 38 75 110 95

Any

4.5 V 8 15 22 19

Any

6 V 6 13 19 16

operating characteristics, T

= 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Power dissipation capacitance per flip-flop No load 35 pF

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