波形发生器
Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
package waveform_pkg is
constant rom_width : integer := 6 ;
subtype rom_word is std_logic_vector ( 1 to rom_width) ;
subtype rom_range is integer range 0 to 12 ;
type rom_table is array ( 0 to 12) of rom_word ;
constant rom_data : rom_table := rom_table'(
"111010" ,
"101000" ,
"011000" ,
"001000" ,
"011010" ,
"010011" ,
"101110" ,
"110100" ,
"001010" ,
"001000" ,
"010110" ,
"010101" ,
"001111" ) ;
subtype data_word is integer range 0 to 100 ;
subtype data_range is integer range 0 to 12 ;
type data_table is array (0 to 12) of data_word ;
constant data : data_table := data_table'(1,40,9,2,2,4,1,15,5,1,1,3,1) ;
end waveform_pkg ;
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_arith.ALL ;
USE work.waveform_pkg.all ;
entity smart_waveform is
port (
clock : in std_logic ;
reset : in boolean ;
waves : out rom_word
) ;
end ;
architecture rtl of smart_waveform is
signal step,next_step : rom_range ;
signal delay : data_word ;
begin
next_step <= rom_range'high when step = rom_range'high else step + 1 ;
time_step : process
begin
wait until clock'event and clock = '1' and clock'last_value = '0';
if (reset) then
step <= 0 ;
elsif (delay = 1) then
step <= next_step ;
else
null ;
end if ;
end process ;
delay_step : process
begin
wait until clock'event and clock = '1' ;
if (reset) then
delay <= data(0) ;
elsif (delay = 1) then
delay <= data(next_step) ;
else
delay <= delay - 1 ;
end if ;
end process ;
waves <= rom_data(step) ;
end ;
加法器源程序
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity adder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end adder;
-- description of adder using concurrent signal assignments
architecture rtl of adder is
begin
sum <= (a xor b) xor cin;
cout <= (a and b) or (cin and a) or (cin and b);
end rtl;
-- description of adder using component instantiation statements
use work.gates.all;
architecture structural of adder is
signal xor1_out,
and1_out,
and2_out,
or1_out : std_logic;
begin
xor1: xorg port map(
in1 => a,
in2 => b,
out1 => xor1_out);
xor2: xorg port map(
in1 => xor1_out,
in2 => cin,
out1 => sum);
and1: andg port map(
in1 => a,
in2 => b,
out1 => and1_out);
or1: org port map(
in1 => a,
in2 => b,
out1 => or1_out);
and2: andg port map(
in1 => cin,
in2 => or1_out,
out1 => and2_out);
or2: org port map(
in1 => and1_out,
in2 => and2_out,
out1 => cout);
end structural;
------------------------------------------------------------------------
-- N-bit adder
-- The width of the adder is determined by generic N
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity adderN is
generic(N : integer := 16);
port (a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);
cin : in std_logic;
sum : out std_logic_vector(N downto 1);
cout : out std_logic);
end adderN;
-- structural implementation of the N-bit adder
architecture structural of adderN is
component adder
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end component;
signal carry : std_logic_vector(0 to N);
begin
carry(0) <= cin;
cout <= carry(N);
-- instantiate a single-bit adder N times
gen: for I in 1 to N generate
add: adder port map(
a => a(I),
b => b(I),
cin => carry(I - 1),
sum => sum(I),
cout => carry(I));
end generate;
end structural;
-- behavioral implementation of the N-bit adder
architecture behavioral of adderN is
begin
p1: process(a, b, cin)
variable vsum : std_logic_vector(N downto 1);
variable carry : std_logic;
begin
carry := cin;
for i in 1 to N loop
vsum(i) := (a(i) xor b(i)) xor carry;
carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));
end loop;
sum <= vsum;
cout <= carry;
end process p1;
end behavioral;
各种功能的计数器
Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
ENTITY counters IS
PORT
(
d : IN INTEGER RANGE 0 TO 255;
clk : IN BIT;
clear : IN BIT;
ld : IN BIT;
enable : IN BIT;
up_down : IN BIT;
qa : OUT INTEGER RANGE 0 TO 255;
qb : OUT INTEGER RANGE 0 TO 255;
qc : OUT INTEGER RANGE 0 TO 255;
qd : OUT INTEGER RANGE 0 TO 255;
qe : OUT INTEGER RANGE 0 TO 255;
qf : OUT INTEGER RANGE 0 TO 255;
qg : OUT INTEGER RANGE 0 TO 255;
qh : OUT INTEGER RANGE 0 TO 255;
qi : OUT INTEGER RANGE 0 TO 255;
qj : OUT INTEGER RANGE 0 TO 255;
qk : OUT INTEGER RANGE 0 TO 255;
ql : OUT INTEGER RANGE 0 TO 255;
qm : OUT INTEGER RANGE 0 TO 255;
qn : OUT INTEGER RANGE 0 TO 255
);
END counters;
ARCHITECTURE a OF counters IS
BEGIN
-- An enable counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF enable = '1' THEN
cnt := cnt + 1;
END IF;
END IF;
qa <= cnt;
END PROCESS;
-- A synchronous load counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + 1;
END IF;
END IF;
qb <= cnt;
END PROCESS;
-- A synchronous clear counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt := 0;
ELSE
cnt := cnt + 1;
END IF;
END IF;
qc <= cnt;
END PROCESS;
-- An up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
cnt := cnt + direction;
END IF;
qd <= cnt;
END PROCESS;
-- A synchronous load enable counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt := d;
ELSE
IF enable = '1' THEN
cnt := cnt + 1;
END IF;
END IF;
END IF;
qe <= cnt;
END PROCESS;
-- An enable up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF enable = '1' THEN
cnt := cnt + direction;
END IF;
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