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《PDIUSBD12与PL2303：USB通信接口详解》 PDIUSBD12和PL2303是两个在嵌入式系统中常用的USB接口芯片，它们在实现设备与电脑之间的数据交换中扮演着关键角色。本文将深入探讨这两个芯片的工作原理、特性以及应用。 PDIUSBD12是由Microchip Technology公司推出的USB到串口桥接器。它是一种低成本、低功耗的解决方案，可将传统的串行接口（如UART）转换为符合USB规范的接口，从而使得非USB设备能够通过USB接口与计算机通信。PDIUSBD12支持全速USB 1.1规范，最高数据传输速率为12Mbps。该芯片内含一个内置的USB协议引擎，可以处理USB主机的数据包，并通过UART接口与微控制器交互，简化了系统设计。 PDIUSBD12的主要特性包括： 1. 自动数据流控制，支持硬件握手（例如RTS/CTS、DTR/DSR）。 2. 内置USB总线电源管理，支持上电和下电检测。 3. 可配置的UART波特率，范围可达300bps到1.5Mbps。 4. 支持中断、控制、批量和同步传输四种USB传输类型。 5. 集成的USB电压调整器，可以为微控制器提供稳定的工作电源。接下来，PL2303是台湾普诚科技（Prolific Technology Inc.）的USB到串口桥接器，同样用于串行设备与USB接口的连接。PL2303支持全速USB 2.0规范，最大数据速率可达480Mbps。相较于PDIUSBD12，PL2303在数据传输速度上有优势，且具有以下特点： 1. 支持多种操作系统，包括Windows、Linux、Mac OS等。 2. 具有硬件数据缓冲区，减少数据丢失风险。 3. 提供多种工作模式，如自动流控、硬件流控和无流控。 4. 内建PHY层，无需额外的USB物理层器件。 5. 强大的错误检测和恢复机制，确保数据传输的可靠性。在实际应用中，PDIUSBD12和PL2303常被用于各种嵌入式系统，如GPS接收器、条形码扫描仪、打印机、Modem等。开发人员需要了解如何配置这些芯片的寄存器以满足特定应用需求，这通常涉及到编程USB设备描述符、配置选择、端点设置等。此外，驱动程序的编写也是关键，因为它们是连接硬件与操作系统之间的桥梁。在提供的“PDIUSBD12.PDF”文档中，读者可以找到关于PDIUSBD12芯片的详细规格、引脚描述、功能框图、电路设计示例以及应用指南等内容，这些都是理解和使用PDIUSBD12芯片的重要参考资料。对于想深入学习USB通信接口的开发者来说，这份资料无疑是宝贵的资源。总结，PDIUSBD12和PL2303都是在USB通信领域中不可或缺的组件。理解它们的工作原理和特性，能帮助我们更好地设计和实现USB设备，提升系统的兼容性和性能。而提供的PDF文档则为开发者提供了官方的详细指导，是学习和使用PDIUSBD12芯片的宝贵资料。

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PDIUSBD12

USB interface device with parallel bus

Rev. 08 — 20 December 2001 Product data

1. Description

The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in

microcontroller based systems and communicates with the system microcontroller

over the high-speed general purpose parallel interface. It also supports local DMA

transfer.

This modular approach to implementing a USB interface allows the designer to

choose the optimum system microcontroller from the available wide variety. This

ﬂexibility cuts down the development time, risks, and costs by allowing the use of the

existing architecture and minimize ﬁrmware investments. This results in the fastest

way to develop the most cost effective USB peripheral solution.

The PDIUSBD12 fully conforms to the

USB speciﬁcation Rev. 2.0 (basic speed)

. It is

also designed to be compliant with most device class speciﬁcations: Imaging Class,

Mass Storage Devices, Communication Devices, Printing Devices, and Human

Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like

Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers

an immediate cost reduction for applications that currently use SCSI

implementations.

The PDIUSBD12 low suspend power consumption along with the LazyClock output

allows for easy implementation of equipment that is compliant to the ACPI™,

OnNOW™, and USB power management requirements. The low operating power

allows the implementation of bus powered peripherals.

In addition, it also incorporates features like SoftConnect™, GoodLink™,

programmable clock output, low frequency crystal oscillator, and integration of

termination resistors. All of these features contribute to signiﬁcant cost savings in the

system implementation and at the same time ease the implementation of advanced

USB functionality into the peripherals.

2. Features

■ Complies with the

Universal Serial Bus speciﬁcation Rev. 2.0 (basic speed)

■ High performance USB interface device with integrated SIE, FIFO memory,

transceiver and voltage regulator

■ Compliant with most Device Class speciﬁcations

■ High-speed (2 Mbytes/s) parallel interface to any external microcontroller or

microprocessor

■ Fully autonomous DMA operation

■ Integrated 320 bytes of multi-conﬁguration FIFO memory

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

Product data Rev. 08 — 20 December 2001 2 of 35

9397 750 09238

■ Double buffering scheme for main endpoint increases throughput and eases

real-time data transfer

■ Data transfer rates: 1 Mbytes/s achievable in Bulk mode, 1 Mbits/s achievable in

Isochronous mode

■ Bus-powered capability with very good EMI performance

■ Controllable LazyClock output during suspend

■ Software controllable connection to the USB bus (SoftConnect™)

■ Good USB connection indicator that blinks with trafﬁc (GoodLink™)

■ Programmable clock frequency output

■ Complies with the ACPI, OnNOW and USB power management requirements

■ Internal Power-on reset and low-voltage reset circuit

■ Available in SO28 and TSSOP28 pin packages

■ Full industrial grade operation from −40 to +85 °C

■ Higher than 8 kV in-circuit ESD protection lowers cost of extra components

■ Full-scan design with high fault coverage (>99%) ensures high quality

■ Operation with dual voltages:

3.3 ±0.3 V or extended 5 V supply range of 4.0 to 5.5 V

■ Multiple interrupt modes to facilitate both bulk and isochronous transfers.

3. Pinning information

3.1 Pinning

Fig 1. Pin conﬁguration.

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

Product data Rev. 08 — 20 December 2001 3 of 35

9397 750 09238

3.2 Pin description

Table 1: Pin description

Symbol Pin Type

[1]

Description

DATA <0> 1 IO2 Bit 0 of bidirectional data. Slew-rate controlled.

DATA <1> 2 IO2 Bit 1 of bidirectional data. Slew-rate controlled.

DATA <2> 3 IO2 Bit 2 of bidirectional data. Slew-rate controlled.

DATA <3> 4 IO2 Bit 3 of bidirectional data. Slew-rate controlled.

GND 5 P Ground.

DATA <4> 6 IO2 Bit 4 of bidirectional data. Slew-rate controlled.

DATA <5> 7 IO2 Bit 5 of bidirectional data. Slew-rate controlled.

DATA <6> 8 IO2 Bit 6 of bidirectional data. Slew-rate controlled.

DATA <7> 9 IO2 Bit 7 of bidirectional data. Slew-rate controlled.

ALE 10 I Address Latch Enable. The falling edge is used to close the

latch of the address information in a multiplexed address/ data

bus. Permanently tied LOW for separate address/ data bus

conﬁguration.

CS_N 11 I Chip Select (Active LOW).

SUSPEND 12 I,OD4 Device is in Suspend state.

CLKOUT 13 O2 Programmable Output Clock (slew-rate controlled).

INT_N 14 OD4 Interrupt (Active LOW).

RD_N 15 I Read Strobe (Active LOW).

WR_N 16 I Write Strobe (Active LOW).

DMREQ 17 O4 DMA Request.

DMACK_N 18 I DMA Acknowledge (Active LOW).

EOT_N 19 I End of DMA Transfer (Active LOW). Double up as V

BUS

sensing.

EOT_N is only valid when asserted together with DMACK_N

and either RD_N or WR_N.

RESET_N 20 I Reset (Active LOW and asynchronous). Built-in Power-on reset

circuit present on chip, so pin can be tied HIGH to V

GL_N 21 OD8 GoodLink LED indicator (Active LOW)

XTAL1 22 I Crystal Connection 1 (6 MHz).

XTAL2 23 O Crystal Connection 2 (6 MHz). If external clock signal, instead

of crystal, is connected to XTAL1, then XTAL2 should be

ﬂoated.

24 P Voltage supply (4.0 − 5.5 V).

To operate the IC at 3.3 V, supply 3.3 V to both V

and V

OUT3.3

pins.

D− 25 A USB D− data line.

D+ 26 A USB D+ data line.

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

Product data Rev. 08 — 20 December 2001 4 of 35

9397 750 09238

[1] O2 : Output with 2 mA drive

OD4: Output Open Drain with 4 mA drive

OD8: Output Open Drain with 8 mA drive

IO2: Input and Output with 2 mA drive

O4 : Output with 4 mA drive.

4. Ordering information

5. Block diagram

OUT3.3

27 P 3.3 V regulated output. To operate the IC at 3.3 V, supply a

3.3 V to both V

and V

OUT3.3

pins.

A0 28 I Address bit. A0 = 1 selects command instruction; A0 = 0 selects

the data phase. This bit is a don’t care in a multiplexed address

and data bus conﬁguration and should be tied HIGH.

Table 1: Pin description

…continued

Symbol Pin Type

[1]

Description

Table 2: Ordering information

Packages Temperature range Outside North America North America Pkg. Dwg. #

28-pin plastic SO −40 °C to +85 °C PDIUSBD12 D PDIUSBD12 D SOT136-1

28-pin plastic TSSOP −40 °C to +85 °C PDIUSBD12 PW PDIUSBD12PW DH SOT361-1

This is a conceptual block diagram and does not include each individual signal.

Fig 2. Block diagram.

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

Product data Rev. 08 — 20 December 2001 5 of 35

9397 750 09238

6. Functional description

6.1 Analog transceiver

The integrated transceiver interfaces directly to the USB cables through termination

resistors.

6.2 Voltage regulator

A 3.3 V regulator is integrated on-chip to supply the analog transceiver. This voltage

is also provided as an output to connect to the external 1.5 kΩ pull-up resistor.

Alternatively, the PDIUSBD12 provides SoftConnect technology with an integrated

1.5 kΩ pull-up resistor.

6.3 PLL

A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip.

This allows for the use of a low-cost 6 MHz crystal. EMI is also minimized due to the

lower frequency crystal. No external components are needed for the operation of the

PLL.

6.4 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream

using 4× oversampling principle. It is able to track jitter and frequency drift speciﬁed

by the USB speciﬁcation.

6.5 Philips Serial Interface Engine (PSIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no ﬁrmware intervention. The functions of this block include:

synchronization pattern recognition, parallel/serial conversion, bit stufﬁng/de-stufﬁng,

CRC checking/generation, PID veriﬁcation/generation, address recognition, and

handshake evaluation/generation.

6.6 SoftConnect

The connection to the USB is accomplished by bringing D+ (for high-speed USB

device) HIGH through a 1.5 kΩ pull-up resistor. In the PDIUSBD12, the 1.5 kΩ pull-up

resistor is integrated on-chip and is not connected to V

by default. The connection

is established through a command sent by the external/system microcontroller. This

allows the system microcontroller to complete its initialization sequence before

deciding to establish connection to the USB. Re-initialization of the USB bus

connection can also be performed without requiring to pull out the cable.

The PDIUSBD12 will check for USB V

BUS

availability before the connection can be

established. V

BUS

sensing is provided through pin EOT_N. See Section 3.2 “Pin

description” for details. Sharing of V

BUS

sensing and EOT_N can be easily

accomplished by using V

BUS

voltage as the pull-up voltage for the normally

open-drain output of the DMA controller pin.

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