LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fq_divider IS
generic(n:integer:=60000);
PORT(
CLK,reset: IN STD_LOGIC;
CLK_OUT:buffer STD_LOGIC
);
END;
ARCHITECTURE A OF fq_divider IS
SIGNAL CNT1,CNT2:integer:=0;
SIGNAL OUTTEMP:STD_LOGIC;
SIGNAL LOUT:STD_LOGIC;
SIGNAL OUT3:STD_LOGIC:='0';
BEGIN
P1:PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT1=n-1 THEN
CNT1<=0;
ELSE
CNT1<=CNT1+1;
END IF;
END IF;
END PROCESS P1;
P2:PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='0' THEN
IF CNT2=n-1 THEN
CNT2<=0;
ELSE
CNT2<=CNT2+1;
END IF;
END IF;
END PROCESS P2;
P3:PROCESS(CNT1,CNT2 )
BEGIN
if ((n mod 2)=1) then
IF CNT1=1 THEN
IF CNT2=0 THEN
OUTTEMP<='1';
ELSE
OUTTEMP<='0';
END IF;
ELSIF CNT1=(n+1)/2 THEN
IF CNT2=(n+1)/2 THEN
OUTTEMP<='1';
ELSE OUTTEMP<='0';
END IF;
ELSE
OUTTEMP<='0';
END IF;
else
if cnt1=1 then
outtemp<='1';
elsif (cnt1=(n/2+1)) then
outtemp<='1';
else
outtemp<='0';
end if;
end if;
END PROCESS P3;
P4:PROCESS(OUTTEMP,clk,reset)
BEGIN
if reset='0' then
clk_out<=clk;
elsif ((n/=2) and (n/=1)) then
IF OUTTEMP'EVENT AND OUTTEMP='1' THEN
CLK_OUT<=NOT CLK_OUT;
END IF;
elsif (n=2) then
if(clk'event and clk='1')then
clk_out<=not clk_out;
end if;
else
clk_out<=clk;
end if;
END PROCESS P4;
END A;
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