#include <ccblkfn.h>
#include <cdefBF533.h>
#include <sysreg.h>
#include <stdio.h>
#include "gen_func.h"
#include "adc.h"
short RxBuffer[5];
void Init_Sport1(void)
{
*pSPORT1_RCLKDIV = 0x0250;
*pSPORT1_RFSDIV = 0x000F;
*pSPORT1_RCR1 = RFSR|IRCLK|IRFS| RCKFE;
*pSPORT1_RCR2 = SLEN_16;
}
void Init_sport1_DMA(void)
{
*pDMA3_PERIPHERAL_MAP = 0x3000; // Map DMA1 to Sport1 RX
*pDMA3_CONFIG = WNR | WDSIZE_16 | DI_EN ;//| FLOW_1;
*pDMA3_START_ADDR = (void *)RxBuffer;// Start address of data buffer
*pDMA3_X_COUNT =6;// DMA inner loop count
*pDMA3_X_MODIFY = 2;// Inner loop address increment
}
void Init_Sport1_Interrupts(void)
{
*pSIC_IAR0 = 0xffffffff;// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9
*pSIC_IAR1 = 0xffff2fff;
*pSIC_IAR2 = 0xffffffff;
// register_handler(ik_ivg9, Sport1_RX_ISR);
*pSIC_IMASK = 0x00000800;
ssync();
}
void AD_Read(void)
{
*pDMA3_CONFIG = (*pDMA3_CONFIG | DMAEN);// enable Sport1 RXb
*pSPORT1_RCR1 = (*pSPORT1_RCR1 | RSPEN);
ssync();
}
void ADc_Exp(void)
{
Init_Sport1();
Init_Sport1_Interrupts();
Init_sport1_DMA();
AD_Read();
}
//EX_INTERRUPT_HANDLER(Sport1_RX_ISR)
//{
//*pDMA3_IRQ_STATUS |= 0x0001; // Write 1 to clear
//}
