PWN.rar_PWN

#include <C8051F120.H> void SYSCLK_Init0 (void)//11。0592MHz晶振8倍频 { int i; // delay counter char old_SFRPAGE = SFRPAGE; // Store current SFRPAGE SFRPAGE = CONFIG_PAGE; // set SFR page OSCXCN = 0x67; // start external oscillator with // 11.0592MHz crystal for (i=0; i < 256; i++) ; // Wait for osc. to start up while (!(OSCXCN & 0x80)) ; // Wait for crystal osc. to settle CLKSEL = 0x01; // Select the external osc. as // the SYSCLK source OSCICN = 0x00; // Disable the internal osc. //Turn on the PLL and increase the system clock by a factor of M/N = 16/2 = 8 SFRPAGE = PLL0_PAGE; PLL0CN = 0x04; // Set PLL source as external osc. SFRPAGE = LEGACY_PAGE; FLSCL = 0x30; // Set FLASH read time for 100MHz clk // or less SFRPAGE = PLL0_PAGE; PLL0CN |= 0x01; // Enable Power to PLL PLL0DIV = 0x02; // Set Pre-divide value to N (N = 2) PLL0FLT = 0x0f; // Set the PLL filter register for // a reference clock from 5 - 8 MHz // and an output clock from 60 - 100 MHz PLL0MUL = 0x10; // Multiply SYSCLK by M (M = 16) for (i=0; i < 256; i++) ; // Wait at least 5us for (i=0; i < 256; i++) ; PLL0CN |= 0x02; // Enable the PLL while(!(PLL0CN & 0x10)); // Wait until PLL frequency is locked CLKSEL = 0x02; // Select PLL as SYSCLK source SFRPAGE = old_SFRPAGE; // restore SFRPAGE } void PORT_Init (void) { WDTCN = 0xde; WDTCN = 0xad; SYSCLK_Init0(); SFRPAGE=0xf; XBR0=0x08; XBR2=0x40; P0MDOUT=0x01; } void PWN_Init (int a) { char old_SFRPAGE=SFRPAGE; SFRPAGE=0x0; PCA0CN=0x40; //允许PCA0定时器 PCA0MD=0x01; //系统时钟12 分频作为基准时钟 //允许PCA0定时器溢出中断请求 PCA0CPM0=0X4b;//设置8位PWM 方式 //使能比较器ECOM0 PCA0CPH0=a; //控制占空比 EIE1=0x08; IE=0x80; //开启PWN中断 SFRPAGE = old_SFRPAGE; } void main() { PORT_Init (); PWN_Init(200); while(1); } void PWN() interrupt 9 { char old_SFRPAGE = SFRPAGE; SFRPAGE = 0x00; PCA0CN&=0x40; //清零PCA定时器溢出标志CF SFRPAGE = old_SFRPAGE; }