88-560 Reconfigurable
Computing
Assignment #2
Digital System Modeling,
Simulation and Synthesis for
FPGAs
Ran Wang (103680503)
Yuan Tian (103657282)
The project is consists of three parts which are MEMORY , CONTROL and ALU
modules. The clock connects to the MEMORY, CONTROL and two registers in ALU
which are X_REG and Y_REG.
MEMORY: the memory module contains 256 words. Each word is 8_bits wide. A
location in the memory can be written by placing an 8-bit address on the ADDR
input and placing a ‘1’ on the W/R input when the clock makes a transition from
‘0’ to ‘1’. To read from the memory W/R should be set to ’0’ and an address
should be placed onto the MAINBUS. When MEMDRIVE is ‘0’, the memory does
not drive the MAINBUS.
This is the graph showing the simulation result of the memory . The first period of
clock the value in the address of 2 is read into output and then write the input
into address 2. The result turns out to be right.
ALU: the ALU consists of two internal registers and some purely combinational
math logic. Each of the registers is 8-bits wide. If the LD_X signal is ‘1’ when the
clock rises from ‘0’ to ‘1’ then the value on MAINBUS is loaded into X_REG. Y_REG
behaves in a similar way. The ALU can perform four arithmetic and four logical
functions as described in Table 1. The ALLU function is selected by the bits placed
on the FUNCT signal which is 3_bits wide. The ALU also has an input called
ALUDRIVE. If ALUDRIVE is ‘1’ then the output of MATH_LOGIC is driven onto the
MAINBUS. If ALUDRIVE IS ‘0’ then the MATH_LOGIC output does not drive the bus
and should be in the high-impedance state ‘Z’.
