library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clk_counter is
port (osc_clk :in std_logic;
clk_div:buffer std_logic;
seg:out std_logic_vector(7 downto 0));
end clk_counter;
architecture bhv of clk_counter is
signal clk_cnt:integer range 0 to 2048000;
signal q:std_logic_vector(3 downto 0);
begin
process (osc_clk)
begin
if (osc_clk'event and osc_clk='1')then
clk_cnt<=clk_cnt+1;
end if ;
end process;
clk_div<='1' when clk_cnt=2048000 else '0';
process (clk_div)
begin
if(clk_div'event and clk_div='1') then
if q>3 then q<="0000";else
q<=q+1;
end if;
end if;
end process;
process(q)
begin
case q is
when "0000"=>seg<="00000011";
when "0001"=>seg<="10011111";
when "0010"=>seg<="00100101";
when "0011"=>seg<="11110010";
when "0100"=>seg<="10011001";
when "0101"=>seg<="01001001";
when "0110"=>seg<="01000011";
when "0111"=>seg<="00011111";
when "1000"=>seg<="00000001";
when "1001"=>seg<="00001001";
when others=>seg<="11111111";
end case;
end process;
end bhv;
