®
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©2009 Integrated Device Technology, Inc.
Tsi107
™
User Manual
80C2000_MA001_05
November 2009
GENERAL DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
CODE DISCLAIMER
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at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICU-
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CONTENTS
Paragraph
Number
Title
Page
Number
IDT iii
About This Book
Audience ......................................................................................................... xxxvii
Organization................................................................................................... xxxviii
Suggested Reading........................................................................................... xxxix
Conventions .......................................................................................................... xli
Acronyms and Abbreviations .............................................................................. xlii
Revision History ................................................................................................. xliii
Chapter 1
Overview
1.1 Tsi107 PowerPC Host Bridge Features .............................................................. 1-1
1.2 Tsi107 PowerPC Host Bridge Applications ...................................................... 1-3
1.3 Tsi107 Major Functional Blocks ........................................................................ 1-6
1.3.1 60x Processor Interface................................................................................... 1-7
1.3.2 Memory System Interface............................................................................... 1-8
1.3.3 Peripheral Component Interconnect (PCI) Interface ...................................... 1-8
1.3.3.1 PCI Bus Arbitration Unit............................................................................ 1-9
1.3.3.2 Address Maps and Translation ................................................................... 1-9
1.3.3.3 Byte Ordering ............................................................................................. 1-9
1.3.3.4 PCI Agent Capability................................................................................ 1-10
1.3.4 DMA Controller............................................................................................ 1-10
1.3.5 Message Unit (MU) ...................................................................................... 1-10
1.3.5.1 Doorbell Registers .................................................................................... 1-10
1.3.5.2 Extended Doorbell Register Facility ........................................................ 1-11
1.3.5.3 Inbound and Outbound Message Registers .............................................. 1-11
1.3.5.4 Intelligent Input/Output Controller (I
2
O) ................................................. 1-11
1.3.6 Inter-Integrated Circuit (I
2
C) Controller ...................................................... 1-11
1.3.7 Embedded Programmable Interrupt Controller (EPIC)................................ 1-12
1.3.8 Integrated PCI Bus, CPU, and SDRAM Clock Generation.......................... 1-12
1.4 Power Management .......................................................................................... 1-13
1.5 Programmable I/O Signals with Watchpoint.................................................... 1-14
1.6 Debug Features ................................................................................................. 1-14
1.6.1 Error Injection/Capture on Data Path ........................................................... 1-14
iv Tsi107 PowerPC Host Bridge User Manual IDT
CONTENTS
Paragraph
Number
Title
Page
Number
1.6.2 IEEE 1149.1 (JTAG)/Test Interface............................................................. 1-14
Chapter 2
Signal Descriptions and Clocking
2.1 Signal Overview ................................................................................................. 2-2
2.1.1 Signal Cross Reference................................................................................... 2-4
2.1.2 Output Signal States during Reset .................................................................. 2-6
2.2 Detailed Signal Descriptions .............................................................................. 2-8
2.2.1 60x Processor Interface Signals...................................................................... 2-8
2.2.1.1 Bus Request 0–1 (BR
[0:1])—Input............................................................ 2-8
2.2.1.2 Bus Grant 0–1 (BG[0:1])—Output............................................................. 2-8
2.2.1.3 Address Bus (A[0:31])................................................................................ 2-9
2.2.1.3.1 Address Bus (A[0:31])—Output ............................................................ 2-9
2.2.1.3.2 Address Bus (A[0:31])—Input............................................................... 2-9
2.2.1.4 Transfer Start (TS)...................................................................................... 2-9
2.2.1.4.1 Transfer Start (TS)—Output................................................................... 2-9
2.2.1.4.2 Transfer Start (TS)—Input ................................................................... 2-10
2.2.1.5 Transfer Type (TT[0:4]) ........................................................................... 2-10
2.2.1.5.1 Transfer Type (TT[0:4])—Output........................................................ 2-10
2.2.1.5.2 Transfer Type (TT[0:4])—Input........................................................... 2-11
2.2.1.6 Transfer Size (TSIZ[0:2])......................................................................... 2-11
2.2.1.6.1 Transfer Size (TSIZ[0:2])—Output...................................................... 2-11
2.2.1.6.2 Transfer Size (TSIZ[0:2])—Input ........................................................ 2-11
2.2.1.7 Transfer Burst (TBST).............................................................................. 2-11
2.2.1.7.1 Transfer Burst (TBST)—Output .......................................................... 2-11
2.2.1.7.2 Transfer Burst (TBST
)—Input............................................................. 2-12
2.2.1.8 Write-Through (WT)—Input/Output........................................................ 2-12
2.2.1.9 Caching-Inhibited (CI
)—Input/Output..................................................... 2-12
2.2.1.10 Global (GBL
)—Input/Output................................................................... 2-12
2.2.1.11 Address Acknowledge (AACK)—Output................................................ 2-13
2.2.1.12 Address Retry (ARTRY)........................................................................... 2-13
2.2.1.12.1 Address Retry (ARTRY
)—Output ....................................................... 2-13
2.2.1.12.2 Address Retry (ARTRY
)—Input.......................................................... 2-14
2.2.1.13 Data Bus Grant 0–1 (DBG[0:1])—Output ............................................... 2-14
2.2.1.14 Data Bus (DH[0:31], DL[0:31]) ............................................................... 2-15
2.2.1.14.1 Data Bus (DH[0:31], DL[0:31])—Output............................................ 2-15
2.2.1.14.2 Data Bus (DH[0:31], DL[0:31])—Input............................................... 2-16
2.2.1.15 Data Parity (DP[0:7])................................................................................ 2-16
2.2.1.15.1 Data Parity (DP[0:7])—Output ............................................................ 2-16
2.2.1.15.2 Data Parity (DP[0:7])—Input............................................................... 2-16
2.2.1.16 Transfer Acknowledge (TA)..................................................................... 2-17
CONTENTS
Paragraph
Number
Title
Page
Number
IDT v
2.2.1.16.1 Transfer Acknowledge (TA)—Output.................................................. 2-17
2.2.1.16.2 Transfer Acknowledge (TA
)—Input .................................................... 2-17
2.2.1.17 Local Bus Slave Claim (LBCLAIM
)—Input ........................................... 2-18
2.2.1.18 Data Bus Grant Local Bus Slave (DBGLB)—Output.............................. 2-18
2.2.2 PCI Interface Signals .................................................................................... 2-18
2.2.2.1 PCI Bus Request (REQ[4:0])—Input....................................................... 2-18
2.2.2.1.1 PCI Bus Request (REQ[4:0])—Internal Arbiter Enabled .................... 2-19
2.2.2.1.2 PCI Bus Request (REQ
[4:0])—Internal Arbiter Disabled ................... 2-19
2.2.2.2 PCI Bus Grant (GNT
[4:0])—Output........................................................ 2-19
2.2.2.2.1 PCI Bus Grant (GNT[4:0])—Internal Arbiter Enabled........................ 2-19
2.2.2.2.2 PCI Bus Grant (GNT
[4:0])—Internal Arbiter Disabled....................... 2-20
2.2.2.3 PCI Address/Data Bus (AD[31:0])........................................................... 2-20
2.2.2.3.1 Address/Data (AD[31:0])—Output...................................................... 2-20
2.2.2.3.2 Address/Data (AD[31:0])—Input......................................................... 2-20
2.2.2.4 Parity (PAR) ............................................................................................. 2-21
2.2.2.4.1 Parity (PAR)—Output.......................................................................... 2-21
2.2.2.4.2 Parity (PAR)—Input............................................................................. 2-21
2.2.2.5 Command/Byte Enable (C/BE
[3:0])......................................................... 2-21
2.2.2.5.1 Command/Byte Enable (C/BE[3:0])—Output ..................................... 2-21
2.2.2.5.2 Command/Byte Enable (C/BE[3:0])—Input........................................ 2-22
2.2.2.6 Device Select (DEVSEL) ......................................................................... 2-22
2.2.2.6.1 Device Select (DEVSEL)—Output...................................................... 2-22
2.2.2.6.2 Device Select (DEVSEL)—Input......................................................... 2-23
2.2.2.7 Frame (FRAME)....................................................................................... 2-23
2.2.2.7.1 Frame (FRAME)—Output ................................................................... 2-23
2.2.2.7.2 Frame (FRAME)—Input...................................................................... 2-23
2.2.2.8 Initiator Ready (IRDY)............................................................................. 2-23
2.2.2.8.1 Initiator Ready (IRDY)—Output.......................................................... 2-23
2.2.2.8.2 Initiator Ready (IRDY
)—Input ............................................................ 2-24
2.2.2.9 Lock (LOCK)—Input............................................................................... 2-24
2.2.2.10 Target Ready (TRDY).............................................................................. 2-24
2.2.2.10.1 Target Ready (TRDY
)—Output........................................................... 2-24
2.2.2.10.2 Target Ready (TRDY
)—Input.............................................................. 2-25
2.2.2.11 Parity Error (PERR).................................................................................. 2-25
2.2.2.11.1 Parity Error (PERR
)—Output .............................................................. 2-25
2.2.2.11.2 Parity Error (PERR
)—Input................................................................. 2-25
2.2.2.12 System Error (SERR) ............................................................................... 2-25
2.2.2.12.1 System Error (SERR
)—Output ............................................................ 2-26
2.2.2.12.2 System Error (SERR
)—Input............................................................... 2-26
2.2.2.13 Stop (STOP
).............................................................................................. 2-26
2.2.2.13.1 Stop (STOP
)—Output .......................................................................... 2-26
2.2.2.13.2 Stop (STOP)—Input............................................................................. 2-26
2.2.2.14 Interrupt Request (INTA
)—Output .......................................................... 2-26
