module shizhong(clk,clk_1,r_st);
input clk,r_st;
output clk_1;
reg[24:0]cnt;// = 25'b0;
reg clk_1;
always @(posedge clk or negedge r_st)
begin
if(!r_st)begin
cnt<=0;
end
else if(cnt == 25'd50000)
begin
cnt <= 25'd0;
end
else cnt <= cnt + 1'b1;
end
always @(posedge clk or negedge r_st)
begin
if(!r_st) begin
clk_1<=0;
end
else if(cnt == 25'd25000)
clk_1 <= ~clk_1;
end
endmodule
module key_switch(
switch,
sign_pluse,
key_data
);
shizhong vv(clk,clk_1,r_st);
wire clk_1;
input [9:0] switch;
output [3:0]key_data;
output reg sign_pluse;
reg [3:0]key_data= 4'b1111;
reg [7:0] cnt;
wire trigger_done;// = (&switch);
assign trigger_done = &switch;
always @(posedge clk_1)
begin
if(trigger_done == 1'b1)
begin
sign_pluse = 1;
cnt = 8'd255;
end
else if((cnt < 200) & (cnt > 100))begin
cnt <= cnt -1'b1;
sign_pluse = 0;
end
else if(cnt == 8'd0)begin
cnt = 8'b0;
sign_pluse = 1;
end
else cnt <= cnt - 1'b1;
end
always @(switch)
begin
case({switch})
10'b11_1111_1110:key_data = 4'b0000;
10'b11_1111_1101:key_data = 4'b0001;
10'b11_1111_1011:key_data = 4'b0010;
10'b11_1111_0111:key_data = 4'b0011;
10'b11_1110_1111:key_data = 4'b0100;
10'b11_1101_1111:key_data = 4'b0101;
10'b11_1011_1111:key_data = 4'b0110;
10'b11_0111_1111:key_data = 4'b0111;
10'b10_1111_1111:key_data = 4'b1000;
10'b01_1111_1111:key_data = 4'b1001;
default key_data = 4'b1111;
endcase
end
endmodule
module key(r_st,key_data,user_ok,code_ok,en, data_user, data_code,cnt_num);
//input sign_pluse;
input [3:0] key_data;
input r_st;
input en;
output reg [11:0] data_user= 24'b0;
output reg [23:0] data_code= 12'b0;
output [5:0]cnt_num;
output reg user_ok,code_ok;
reg [5:0] cnt_num = 0;
reg [3:0]data1= 4'b1111,
data2= 4'b1111,
data3= 4'b1111,
data4= 4'b1111,
data5= 4'b1111,
data6= 4'b1111,
data7= 4'b1111,
data8= 4'b1111,
data9= 4'b1111;
reg [5:0] user_num = 0;
always @(key_data)
begin
data_user = {data9,data8,data7};
data_code = {data6,data5,data4,data3,data2,data1};
case (cnt_num)
4'b0000: data9 = key_data;
4'b0001: data8 = key_data;
4'b0010: data7 = key_data;
4'b0011: data6 = key_data;
4'b0100: data5 = key_data;
4'b0101: data4 = key_data;
4'b0110: data3 = key_data;
4'b0111: data2 = key_data;
4'b1000: data1 = key_data;
default: data9 = 4'b1111;
endcase
cnt_num <= cnt_num +1'b1; end
always @(*)
begin
case({data_user[11:0]})
12'b0001_0000_0001:begin user_num = 4'd1;user_ok =1'b1; end//101
12'b0010_0000_0010:begin user_num = 4'd2;user_ok =1'b1; end//202
12'b0011_0000_0010:begin user_num = 4'd3;user_ok =1'b1; end//312
12'b0100_0000_0101:begin user_num = 4'd4;user_ok =1'b1; end//405
12'b0101_0000_0101:begin user_num = 4'd5;user_ok =1'b1; end//505
12'b0110_0000_0001:begin user_num = 4'd6;user_ok =1'b1; end//601
default: user_ok =1'b0;
endcase
end
always @(*)
begin
case({user_num,data_code[23:0]})
30'b0001_0011_0001_0010_0111_0110_0101:code_ok=1'b1;//1312765
30'b0010_0010_0001_0111_1000_1000_0010:code_ok=1'b1;//2217882
30'b0011_1001_0111_1000_1001_0100_0001:code_ok=1'b1;//3978941
30'b0100_0100_0101_0111_0110_0111_0010:code_ok=1'b1;//4457672
30'b0101_0100_0110_0100_0110_1000_0001:code_ok=1'b1;//5464681
30'b0110_0110_0010_0111_1000_0010_0101:code_ok=1'b1;//6627825
default:code_ok=1'b0;
endcase
end
endmodule
///////////////////////////////////////////////////////////////////////////////////
module mima(clk,key_data,r_st,user_ok,code_ok,en,data_user,data_code,cnt_num);
input r_st,en,clk;
//input [9:0] switch;
input [3:0]key_data;
output user_ok;
output code_ok;
output [11:0] data_user;
output [23:0] data_code;
output [5:0]cnt_num;
//output[5:0]cnt;
//output [7:0]dig;
//output [7:0]seg;
//output clk_1;
//wire [3:0]key_data;
//wire sign_pluse;
//wire clk_1;
//shizhong sz(.clk(clk),.clk_1(clk_1),.r_st(r_st));
//key_switch ks(.clk_1(clk_1),.switch(switch),.key_data(key_data));
key k(.key_data(key_data),.r_st(r_st),.user_ok(user_ok),.code_ok(code_ok),.en(en),
.data_user(data_user),.data_code(data_code),.cnt_num(cnt_num));
//xianshi xs(.cnt(cnt),.r_st(r_st),.clk(clk),.dig(dig),.seg(seg),.user_ok(user_ok),.code_ok//(code_ok));
endmodule
////////////////////////////////////////////////////////////////
module stimulate;
reg clk,r_st,en;
reg [3:0]key_data;
wire [11:0]data_user;
wire [23:0]data_code;
wire [5:0]cnt_num;
//reg [9:0]switch;
//wire clk_1;
//wire [3:0]key_data;reg clk,r_st,en;
reg [3:0]key_data;
wire [11:0]data_user;
wire [23:0]data_code;
wire [5:0]cnt_num;
//reg [9:0]switch;
//wire clk_1;
//wire [3:0]key_data;
//wire sign_pluse;
mima test(.cnt_num(cnt_num),.data_user(data_user),.data_code(data_code),
.en(en),.clk(clk),.r_st(r_st),.key_data(key_data),.user_ok(user_ok),.code_ok(code_ok));
initial
begin
clk = 0;
forever #1 clk=~clk;
end
initial
begin
r_st = 0;
en = 0;
//switch = 10'b1111111111;//4457672
#20 r_st = 1;
#20 key_data = 4'd4;
#20 key_data = 4'd0;
#20 key_data = 4'd5;
en = 1'b1;
#20 key_data = 4'd4;
#20 key_data = 4'd5;
#20 key_data = 4'd7;
#20 key_data = 4'd6;
#20 key_data = 4'd7;
#20 key_data = 4'd2;
/*#20 switch = 10'b1111101111;
#10 switch = 10'b1111111111;
#20 switch = 10'b1111111110;
#10 switch = 10'b1111111111;
#20 switch = 10'b1111011111;
#10 switch = 10'b1111111111;
#20 switch = 10'b1111101111;
#10 switch = 10'b1111111111;
#20 switch = 10'b1111011111;
#10 switch = 10'b1111111111;
#20 switch = 10'b1101111111;
#10 switch = 10'b1111111111;
#20 switch = 10'b1110111111;
#10 switch = 10'b1111111111;
#20 switch = 10'b1101111111;
#10 switch = 10'b1111111111;
#20 switch = 10'b1111111011;
#10 switch = 10'b1111111111;
*/end
endmodule