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© November 2008 Altera Corporation Quartus II Handbook Version 8.1 Volume 1: Design and Synthesis

6. Recommended HDL Coding Styles

Introduction

HDL coding styles can have a significant effect on the quality of results that you

achieve for programmable logic designs. Synthesis tools optimize HDL code for both

logic utilization and performance. However, sometimes the best optimizations require

human understanding of the design, and synthesis tools have no information about

the purpose or intent of the design. You are often in the best position to improve your

quality of results.

■ “Inferring Multiplier and DSP Functions from HDL Code” on page 6–6

■ “Inferring Memory Functions from HDL Code” on page 6–11

■ “Coding Guidelines for Registers and Latches” on page 6–34

■ “General Coding Guidelines” on page 6–44

■ “Designing with Low-Level Primitives” on page 6–68

f For additional guidelines about structuring your design, refer to the Design

Recommendations for Altera Devices and the Quartus II Design Assistant chapter in

volume 1 of the Quartus II Handbook. For additional hand-crafted techniques you can

use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera

devices, including a collection of circuit building blocks and related discussions, refer

Many of the Verilog HDL and VHDL examples in this document correspond with

interface, shown in Figure 6–1.

QII51007-8.1.0

6–2 Chapter 6: Recommended HDL Coding Styles

architectures. Using megafunctions instead of coding your own logic saves valuable

design time. Additionally, the Altera-provided megafunctions may offer more

efficient logic synthesis and device implementation. You can scale the megafunction’s

Chapter 6: Recommended HDL Coding Styles 6–3

Instantiating Altera Megafunctions in HDL Code

from HDL Code” on page 6–11 to ensure your HDL code infers the appropriate Altera

megafunction.

features. You can infer or instantiate megafunctions to target some features such as

memory and DSP blocks. You must instantiate megafunctions to target certain device

and high-speed features such as LVDS drivers, PLLs, transceivers, and double-data

rate input/output (DDIO) circuitry.

■ For simple multiplexers and decoders, use array notation (such as out =

■ Avoid division operations where possible. Division is an inherently slow

Instantiating Altera Megafunctions in HDL Code

The following sections describe how to use megafunctions by instantiating them in

your HDL code with the following methods:

■ “Instantiating Megafunctions Using the Port and Parameter Definition”—You can

6–4 Chapter 6: Recommended HDL Coding Styles

Instantiating Altera Megafunctions in HDL Code

Use the MegaWizard Plug-In Manager as described in this section to create

megafunctions in the Quartus II GUI that you can instantiate in your HDL code. The

parameterize megafunctions, and ensures that you set all megafunction parameters

be generated. Depending on which language you choose, the MegaWizard Plug-In

■ ADHL Include File (.inc) that can be used in Text Design Files (.tdf)

■ Quartus II Block Symbol File (.bsf) for schematic designs

■ Verilog HDL module declaration file that can be used when instantiating the

■ If you enable the option to generate a synthesis area and timing estimation netlist,

Chapter 6: Recommended HDL Coding Styles 6–5

Instantiating Altera Megafunctions in HDL Code

certain third-party synthesis tools to better report area and timing estimates. In

addition, synthesis tools can use the timing information to focus timing-driven

To generate the netlist, turn on Generate a synthesis area and timing estimation

netlist on the EDA page of the MegaWizard Plug-In Manager. The netlist file is called

(1) The MegaWizard Plug-In Manager generates either the Verilog HDL, VHDL, or AHDL Variation Wrapper File, depending on the language you