IIR.rar_iir_iir c程序_iir c

#include "f2407_c.h" #include "iirfilt.h" #include "iircoeff.h" #include "math.h" #define PI 3.1415926 #define SIN_NUM 120 //#pragma DATA_SECTION(iir, "iirfilt"); IIR5BIQ16 iir=IIR5BIQ16_DEFAULTS; /* Instance the Filter Object and Initialize */ //#pragma DATA_SECTION(dbuffer,"iirfilt"); int dbuffer[2*IIR_LPF_NBIQ]; /* Create Delay Buffer */ //#pragma DATA_SECTION(coeff, "iirfilt"); int coeff[5*IIR_LPF_NBIQ]=IIR_LPF_COEFF; /* Create Coefficient Buffer and initialize */ int in_wave[SIN_NUM]; int out_wave[SIN_NUM]; int xn,yn; void ini(void); /****************************** MAIN ROUTINE ***************************/ void main(void) { int i; ini(); iir.dbuffer_ptr=dbuffer; /* Object Initialization */ iir.coeff_ptr=coeff; iir.qfmat=IIR_LPF_QFMAT; iir.nbiq=IIR_LPF_NBIQ; iir.isf=IIR_LPF_ISF; iir.init(&iir); for(i=0;i<SIN_NUM;i++) in_wave[i] = 20000*sin((4*PI*i)/SIN_NUM) + 6000*sin((60*PI*i)/SIN_NUM) + 6000*sin((80*PI*i)/SIN_NUM);; for(i=0;i<SIN_NUM;i++) { iir.input=in_wave[i]; iir.calc(&iir); out_wave[i]=iir.output; } while(1); } /****************************** MAIN ROUTINE ***************************/ void ini(void) { /*** Configure the System Control and Status registers ***/ *SCSR1 = 0x00FD; /* bit 15 0: reserved bit 14 0: CLKOUT = CPUCLK bit 13-12 00: IDLE1 selected for low-power mode bit 11-9 000: PLL x4 mode bit 8 0: reserved bit 7 1: 1 = enable ADC module clock bit 6 1: 1 = enable SCI module clock bit 5 1: 1 = enable SPI module clock bit 4 1: 1 = enable CAN module clock bit 3 1: 1 = enable EVB module clock bit 2 1: 1 = enable EVA module clock bit 1 0: reserved bit 0 1: clear the ILLADR bit */ *SCSR2 = (*SCSR2 | 0x000B) & 0x000F; /* bit 15-6 0's: reserved bit 5 0: do NOT clear the WD OVERRIDE bit bit 4 0: XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd bit 3 1: disable the boot ROM, enable the FLASH bit 2 no change MP/MC* bit reflects state of MP/MC* pin bit 1-0 11: 11 = SARAM mapped to prog and data */ /*** Disable the watchdog timer ***/ *WDCR = 0x00E8; /* bits 15-8 0's: reserved bit 7 1: clear WD flag bit 6 1: disable the dog bit 5-3 101: must be written as 101 bit 2-0 000: WDCLK divider = 1 */ /*** Setup external memory interface for LF2407 EVM ***/ WSGR = 0x0000; /* bit 15-11 0's: reserved bit 10-9 00: bus visibility off bit 8-6 001: 1 wait-state for I/O space bit 5-3 000: 0 wait-state for data space bit 2-0 000: 0 wait state for program space */ /*** Setup shared I/O pins ***/ *MCRA = 0x0fc0; /* group A pins */ /* bit 15 0: 0=IOPB7, 1=TCLKINA bit 14 0: 0=IOPB6, 1=TDIRA bit 13 0: 0=IOPB5, 1=T2PWM/T2CMP bit 12 0: 0=IOPB4, 1=T1PWM/T1CMP bit 11 1: 0=IOPB3, 1=PWM6 bit 10 1: 0=IOPB2, 1=PWM5 bit 9 1: 0=IOPB1, 1=PWM4 bit 8 1: 0=IOPB0, 1=PWM3 bit 7 1: 0=IOPA7, 1=PWM2 bit 6 1: 0=IOPA6, 1=PWM1 bit 5 0: 0=IOPA5, 1=CAP3 bit 4 0: 0=IOPA4, 1=CAP2/QEP2 bit 3 0: 0=IOPA3, 1=CAP1/QEP1 bit 2 0: 0=IOPA2, 1=XINT1 bit 1 0: 0=IOPA1, 1=SCIRXD bit 0 0: 0=IOPA0, 1=SCITXD */ *MCRB = 0xFE00; /* group B pins */ /* bit 15 1: 0=reserved, 1=TMS2 (always write as 1) bit 14 1: 0=reserved, 1=TMS (always write as 1) bit 13 1: 0=reserved, 1=TD0 (always write as 1) bit 12 1: 0=reserved, 1=TDI (always write as 1) bit 11 1: 0=reserved, 1=TCK (always write as 1) bit 10 1: 0=reserved, 1=EMU1 (always write as 1) bit 9 1: 0=reserved, 1=EMU0 (always write as 1) bit 8 0: 0=IOPD0, 1=XINT2/ADCSOC bit 7 0: 0=IOPC7, 1=CANRX bit 6 0: 0=IOPC6, 1=CANTX bit 5 0: 0=IOPC5, 1=SPISTE bit 4 0: 0=IOPC4, 1=SPICLK bit 3 0: 0=IOPC3, 1=SPISOMI bit 2 0: 0=IOPC2, 1=SPISIMO bit 1 0: 0=IOPC1, 1=BIO* bit 0 0: 0=IOPC0, 1=W/R* */ *MCRC = 0x0000; /* group C pins */ /* bit 15 0: reserved bit 14 0: 0=IOPF6, 1=IOPF6 bit 13 0: 0=IOPF5, 1=TCLKINB bit 12 0: 0=IOPF4, 1=TDIRB bit 11 0: 0=IOPF3, 1=T4PWM/T4CMP bit 10 0: 0=IOPF2, 1=T3PWM/T3CMP bit 9 0: 0=IOPF1, 1=CAP6 bit 8 0: 0=IOPF0, 1=CAP5/QEP4 bit 7 0: 0=IOPE7, 1=CAP4/QEP3 bit 6 0: 0=IOPE6, 1=PWM12 bit 5 0: 0=IOPE5, 1=PWM11 bit 4 0: 0=IOPE4, 1=PWM10 bit 3 0: 0=IOPE3, 1=PWM9 bit 2 0: 0=IOPE2, 1=PWM8 bit 1 0: 0=IOPE1, 1=PWM7 bit 0 0: 0=IOPE0, 1=CLKOUT */ /*** Setup the core interrupts ***/ *IMR = 0x0000; /* clear the IMR register */ *IFR = 0x003F; /* clear any pending core interrupts */ *IMR = 0x0004; /* enable desired core interrupts (in1,in3)*/ /*** Setup the event manager interrupts ***/ *EVAIFRA = 0xFFFF; /* clear all EVA group A interrupts */ *EVAIFRB = 0xFFFF; /* clear all EVA group B interrupts */ *EVAIFRC = 0xFFFF; /* clear all EVA group C interrupts */ *EVAIMRA = 0x0000; /* enable desired EVA group A interrupts */ *EVAIMRB = 0x0001; /* enable desired EVA group B interrupts ENABLE TIME2*/ *EVAIMRC = 0x0000; /* enable desired EVA group C interrupts */ *EVBIFRA = 0xFFFF; /* clear all EVB group A interrupts */ *EVBIFRB = 0xFFFF; /* clear all EVB group B interrupts */ *EVBIFRC = 0xFFFF; /* clear all EVB group C interrupts */ *EVBIMRA = 0x0000; /* enable desired EVB group A interrupts */ *EVBIMRB = 0x0000; /* enable desired EVB group B interrupts */ *EVBIMRC = 0x0000; /* enable desired EVB group C interrupts */ }