clk-prima2.rar_tree

/* * Clock tree for CSR SiRFprimaII */ #include <linux/module.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> #define SIRFSOC_CLKC_CLK_EN0 0x0000 #define SIRFSOC_CLKC_CLK_EN1 0x0004 #define SIRFSOC_CLKC_REF_CFG 0x0014 #define SIRFSOC_CLKC_CPU_CFG 0x0018 #define SIRFSOC_CLKC_MEM_CFG 0x001c #define SIRFSOC_CLKC_SYS_CFG 0x0020 #define SIRFSOC_CLKC_IO_CFG 0x0024 #define SIRFSOC_CLKC_DSP_CFG 0x0028 #define SIRFSOC_CLKC_GFX_CFG 0x002c #define SIRFSOC_CLKC_MM_CFG 0x0030 #define SIRFSOC_CLKC_LCD_CFG 0x0034 #define SIRFSOC_CLKC_MMC_CFG 0x0038 #define SIRFSOC_CLKC_PLL1_CFG0 0x0040 #define SIRFSOC_CLKC_PLL2_CFG0 0x0044 #define SIRFSOC_CLKC_PLL3_CFG0 0x0048 #define SIRFSOC_CLKC_PLL1_CFG1 0x004c #define SIRFSOC_CLKC_PLL2_CFG1 0x0050 #define SIRFSOC_CLKC_PLL3_CFG1 0x0054 #define SIRFSOC_CLKC_PLL1_CFG2 0x0058 #define SIRFSOC_CLKC_PLL2_CFG2 0x005c #define SIRFSOC_CLKC_PLL3_CFG2 0x0060 #define SIRFSOC_USBPHY_PLL_CTRL 0x0008 #define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) #define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) #define SIRFSOC_USBPHY_PLL_LOCK BIT(3) static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase; #define KHZ 1000 #define MHZ (KHZ * KHZ) /* * SiRFprimaII clock controller * - 2 oscillators: osc-26MHz, rtc-32.768KHz * - 3 standard configurable plls: pll1, pll2 & pll3 * - 2 exclusive plls: usb phy pll and sata phy pll * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia, * display and sdphy. * Each clock domain can select its own clock source from five clock sources, * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source * clock of the group clock. * - dsp domain: gps, mf * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse * - sys domain: security */ struct clk_pll { struct clk_hw hw; unsigned short regofs; /* register offset */ }; #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) struct clk_dmn { struct clk_hw hw; signed char enable_bit; /* enable bit: 0 ~ 63 */ unsigned short regofs; /* register offset */ }; #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw) struct clk_std { struct clk_hw hw; signed char enable_bit; /* enable bit: 0 ~ 63 */ }; #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) static int std_clk_is_enabled(struct clk_hw *hw); static int std_clk_enable(struct clk_hw *hw); static void std_clk_disable(struct clk_hw *hw); static inline unsigned long clkc_readl(unsigned reg) { return readl(sirfsoc_clk_vbase + reg); } static inline void clkc_writel(u32 val, unsigned reg) { writel(val, sirfsoc_clk_vbase + reg); } /* * std pll */ static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { unsigned long fin = parent_rate; struct clk_pll *clk = to_pllclk(hw); u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; if (clkc_readl(regcfg2) & BIT(2)) { /* pll bypass mode */ return fin; } else { /* fout = fin * nf / nr / od */ u32 cfg0 = clkc_readl(clk->regofs); u32 nf = (cfg0 & (BIT(13) - 1)) + 1; u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; WARN_ON(fin % MHZ); return fin / MHZ * nf / nr / od * MHZ; } } static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { unsigned long fin, nf, nr, od; /* * fout = fin * nf / (nr * od); * set od = 1, nr = fin/MHz, so fout = nf * MHz */ rate = rate - rate % MHZ; nf = rate / MHZ; if (nf > BIT(13)) nf = BIT(13); if (nf < 1) nf = 1; fin = *parent_rate; nr = fin / MHZ; if (nr > BIT(6)) nr = BIT(6); od = 1; return fin * nf / (nr * od); } static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pll *clk = to_pllclk(hw); unsigned long fin, nf, nr, od, reg; /* * fout = fin * nf / (nr * od); * set od = 1, nr = fin/MHz, so fout = nf * MHz */ nf = rate / MHZ; if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) return -EINVAL; fin = parent_rate; BUG_ON(fin < MHZ); nr = fin / MHZ; BUG_ON((fin % MHZ) || nr > BIT(6)); od = 1; reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); clkc_writel(reg, clk->regofs); reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; clkc_writel((nf >> 1) - 1, reg); reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; while (!(clkc_readl(reg) & BIT(6))) cpu_relax(); return 0; } static struct clk_ops std_pll_ops = { .recalc_rate = pll_clk_recalc_rate, .round_rate = pll_clk_round_rate, .set_rate = pll_clk_set_rate, }; static const char *pll_clk_parents[] = { "osc", }; static struct clk_init_data clk_pll1_init = { .name = "pll1", .ops = &std_pll_ops, .parent_names = pll_clk_parents, .num_parents = ARRAY_SIZE(pll_clk_parents), }; static struct clk_init_data clk_pll2_init = { .name = "pll2", .ops = &std_pll_ops, .parent_names = pll_clk_parents, .num_parents = ARRAY_SIZE(pll_clk_parents), }; static struct clk_init_data clk_pll3_init = { .name = "pll3", .ops = &std_pll_ops, .parent_names = pll_clk_parents, .num_parents = ARRAY_SIZE(pll_clk_parents), }; static struct clk_pll clk_pll1 = { .regofs = SIRFSOC_CLKC_PLL1_CFG0, .hw = { .init = &clk_pll1_init, }, }; static struct clk_pll clk_pll2 = { .regofs = SIRFSOC_CLKC_PLL2_CFG0, .hw = { .init = &clk_pll2_init, }, }; static struct clk_pll clk_pll3 = { .regofs = SIRFSOC_CLKC_PLL3_CFG0, .hw = { .init = &clk_pll3_init, }, }; /* * usb uses specified pll */ static int usb_pll_clk_enable(struct clk_hw *hw) { u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) & SIRFSOC_USBPHY_PLL_LOCK)) cpu_relax(); return 0; } static void usb_pll_clk_disable(struct clk_hw *clk) { u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); } static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; } static struct clk_ops usb_pll_ops = { .enable = usb_pll_clk_enable, .disable = usb_pll_clk_disable, .recalc_rate = usb_pll_clk_recalc_rate, }; static struct clk_init_data clk_usb_pll_init = { .name = "usb_pll", .ops = &usb_pll_ops, .parent_names = pll_clk_parents, .num_parents = ARRAY_SIZE(pll_clk_parents), }; static struct clk_hw usb_pll_clk_hw = { .init = &clk_usb_pll_init, }; /* * clock domains - cpu, mem, sys/io, dsp, gfx */ static const char *dmn_clk_parents[] = { "rtc", "osc", "pll1", "pll2", "pll3", }; static u8 dmn_clk_get_parent(struct clk_hw *hw) { struct clk_dmn *clk = to_dmnclk(hw); u32 cfg = clkc_readl(clk->regofs); /* parent of io domain can only be pll3 */ if (strcmp(hw->init->name, "io") == 0) return 4; WARN_ON((cfg & (BIT(3) - 1)) > 4); return cfg & (BIT(3) - 1); } static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent) { struct clk_dmn *clk = to_dmnclk(hw); u32 cfg = clkc_readl(clk->regofs); /* parent of io domain can only be pll3 */ if (strcmp(hw->init->name, "io") == 0) return -EINVAL; cfg &= ~(BIT(3) - 1); clkc_writel(cfg | parent, clk->regofs); /* BIT(3) - switching status: 1 - busy, 0 - done */ while (clkc_readl(clk->regofs) & BIT(3)) cpu_relax(); return 0; } static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { unsigned long fin = parent_rate; struct clk_dmn *clk = to_dmncl