CAN_up_main3.rar_DSP can_UP_dsp

; 240x CPU core registers IMR .set 0004h ; Interrupt Mask Register IFR .set 0006h ; Interrupt Flag Register ; System configuration and interrupt registers PIRQR0 .set 7010h ; Peripheral Interrupt Request register 0 PIRQR1 .set 7011h ; Peripheral Interrupt Request register 1 PIRQR2 .set 7012h ; Peripheral Interrupt Request register 2 PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge register 0 PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge register 1 PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge register 2 SCSR1 .set 7018h ; System Control & Status register. 1 SCSR2 .set 7019h ; System Control & Status register. 2 DINR .set 701Ch ; Device Identification Number register PIVR .set 701Eh ; Peripheral Interrupt Vector register ; Watchdog (WD) registers WDCNTR .set 7023h ; WD Counter register WDKEY .set 7025h ; WD Key register WDCR .set 7029h ; WD Control register ; SPI registers SPICCR .set 7040h ; SPI Config Control register SPICTL .set 7041h ; SPI Operation Control register SPISTS .set 7042h ; SPI Status register SPIBRR .set 7044h ; SPI Baud rate control register SPIRXEMU .set 7046h ; SPI Emulation buffer register SPIRXBUF .set 7047h ; SPI Serial receive buffer register SPITXBUF .set 7048h ; SPI Serial transmit buffer register SPIDAT .set 7049h ; SPI Serial data register SPIPRI .set 704Fh ; SPI Priority control register ; SCI registers SCICCR .set 7050h ; SCI Communication control register SCICTL1 .set 7051h ; SCI Control register 1 SCIHBAUD .set 7052h ; SCI Baud Rate MS byte register SCILBAUD .set 7053h ; SCI Baud Rate LS byte register SCICTL2 .set 7054h ; SCI Control register 2 SCIRXST .set 7055h ; SCI Receiver Status register SCIRXEMU .set 7056h ; SCI Emulation Data Buffer register SCIRXBUF .set 7057h ; SCI Receiver Data buffer register SCITXBUF .set 7059h ; SCI Transmit Data buffer register SCIPRI .set 705Fh ; SCI Priority control register ; External interrupt configuration registers XINT1CR .set 7070h ; External interrupt 1 control register XINT2CR .set 7071h ; External interrupt 2 control register ; Digital I/O registers MCRA .set 7090h ; I/O Mux Control Register A MCRB .set 7092h ; I/O Mux Control Register B MCRC .set 7094h ; I/O Mux Control Register C PEDATDIR .set 7095h ; I/O port E Data & Direction register PFDATDIR .set 7096h ; I/O port F Data & Direction register PADATDIR .set 7098h ; I/O port A Data & Direction register PBDATDIR .set 709Ah ; I/O port B Data & Direction register PCDATDIR .set 709Ch ; I/O port C Data & Direction register PDDATDIR .set 709Eh ; I/O port D Data & Direction register ; ADC registers ADCTRL1 .set 70A0h ; ADC Control register 1 ADCTRL2 .set 70A1h ; ADC Control register 2 MAXCONV .set 70A2h ; Maximum conversion channels register CHSELSEQ1 .set 70A3h ; Channel select Sequencing control register 1 CHSELSEQ2 .set 70A4h ; Channel select Sequencing control register 2 CHSELSEQ3 .set 70A5h ; Channel select Sequencing control register 3 CHSELSEQ4 .set 70A6h ; Channel select Sequencing control register 4 AUTO_SEQ_SR .set 70A7h ; Auto–sequence status register RESULT0 .set 70A8h ; Conversion result register 0 RESULT1 .set 70A9h ; Conversion result register 1 RESULT2 .set 70Aah ; Conversion result register 2 RESULT3 .set 70Abh ; Conversion result register 3 RESULT4 .set 70Ach ; Conversion result register 4 RESULT5 .set 70Adh ; Conversion result register 5 RESULT6 .set 70Aeh ; Conversion result register 6 RESULT7 .set 70Afh ; Conversion result register 7 RESULT8 .set 70B0h ; Conversion result register 8 RESULT9 .set 70B1h ; Conversion result register 9 RESULT10 .set 70B2h ; Conversion result register 10 RESULT11 .set 70B3h ; Conversion result register 11 RESULT12 .set 70B4h ; Conversion result register 12 RESULT13 .set 70B5h ; Conversion result register 13 RESULT14 .set 70B6h ; Conversion result register 14 RESULT15 .set 70B7h ; Conversion result register 15 CALIBRATION .set 70B8h ; Calibration result, used to correct subsequent conversions ; CAN registers MDER .set 7100h ; CAN Mailbox Direction/Enable register TCR .set 7101h ; CAN Transmission Control register RCR .set 7102h ; CAN Recieve Control register MCR .set 7103h ; CAN Master Control register BCR2 .set 7104h ; CAN Bit Config register 2 BCR1 .set 7105h ; CAN Bit Config register 1 ESR .set 7106h ; CAN Error Status register GSR .set 7107h ; CAN Global Status register CEC .set 7108h ; CAN Trans and Rcv Err counters CAN_IFR .set 7109h ; CAN Interrupt Flag Register CAN_IMR .set 710ah ; CAN Interrupt Mask Register LAM0_H .set 710bh ; CAN Local Acceptance Mask MBX0/1 LAM0_L .set 710ch ; CAN Local Acceptance Mask MBX0/1 LAM1_H .set 710dh ; CAN Local Acceptance Mask MBX2/3 LAM1_L .set 710eh ; CAN Local Acceptance Mask MBX2/3 ;~~~~~~~~~~~~~~~~~~~~~邮箱#0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MSGID0L .set 7200h ; CAN Message ID for mailbox 0 (lower 16 bits) MSGID0H .set 7201h ; CAN Message ID for mailbox 0 (upper 16 bits) MSGCTRL0 .set 7202h ; CAN RTR and DLC MBX0A .set 7204h ; CAN 2 of 8 bytes of Mailbox 0 MBX0B .set 7205h ; CAN 2 of 8 bytes of Mailbox 0 MBX0C .set 7206h ; CAN 2 of 8 bytes of Mailbox 0 MBX0D .set 7207h ; CAN 2 of 8 bytes of Mailbox 0 ;~~~~~~~~~~~~~~~~~~~~~邮箱#1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MSGID1L .set 7208h ; CAN Message ID for mailbox 1 (lower 16 bits) MSGID1H .set 7209h ; CAN Message ID for mailbox 1 (upper 16 bits) MSGCTRL1 .set 720Ah ; CAN RTR and DLC MBX1A .set 720Ch ; CAN 2 of 8 bytes of Mailbox 1 MBX1B .set 720Dh ; CAN 2 of 8 bytes of Mailbox 1 MBX1C .set 720Eh ; CAN 2 of 8 bytes of Mailbox 1 MBX1D .set 720Fh ; CAN 2 of 8 bytes of Mailbox 1 ;~~~~~~~~~~~~~~~~~~~~~邮箱#2~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MSGID2L .set 7210h ; CAN Message ID for mailbox 2 (lower 16 bits) MSGID2H .set 7211h ; CAN Message ID for mailbox 2 (upper 16 bits) MSGCTRL2 .set 7212h ; CAN RTR and DLC MBX2A .set 7214h ; CAN 2 of 8 bytes of Mailbox 2 MBX2B .set 7215h ; CAN 2 of 8 bytes of Mailbox 2 MBX2C .set 7216h ; CAN 2 of 8 bytes of Mailbox 2 MBX2D .set 7217h ; CAN 2 of 8 bytes of Mailbox 2 ;~~~~~~~~~~~~~~~~~~~~~邮箱#3~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MSGID3L .set 7218h ; CAN Message ID for mailbox 3 (lower 16 bits) MSGID3H .set 7219h ; CAN Message ID for mailbox 3 (upper 16 bits) MSGCTRL3 .set 721Ah ; CAN RTR and DLC MBX3A .set 721Ch ; CAN 2 of 8 bytes of Mailbox 3 MBX3B .set 721Dh ; CAN 2 of 8 bytes of Mailbox 3 MBX3C .set 721Eh ; CAN 2 of 8 bytes of Mailbox 3 MBX3D .set 721Fh ; CAN 2 of 8 bytes of Mailbox 3 ;~~~~~~~~~~~~~~~~~~~~~邮箱#4~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MSGID4L .set 7220h ; CAN Message ID for mailbox 4 (lower 16 bits) MSGID4H .set 7221h ; CAN Message ID for mailbox 4 (upper 16 bits) MSGCTRL4 .set 7222h ; CAN RTR and DLC MBX4A .set 7224h ; CAN 2 of 8 bytes of Mailbox 4 MBX4B .set 7225h ; CAN 2 of 8 bytes of Mailbox 4 MBX4C .set 7226h ; CAN 2 of 8 bytes of Mailbox 4 MBX4D .set 7227h ; CAN 2 of 8 bytes of Mailbox 4 ;~~~~~~~~~~~~~~~~~~~~~邮箱#5~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MSGID5L .set 7228h ; CAN Message ID for mailbox 5 (lower 16 bits) MSGID