; Originator: Texas Instruments
;
; Description: F240 Header file containing all peripheral register
; declarations as well as other useful definitions.
;
; Last Updated: 27 May 1997
;
;***********************************************************************
;-----------------------------------------------------------------------
; On Chip Periperal Register Definitions (All registers mapped into data
; space unless otherwise noted)
;-----------------------------------------------------------------------
;Global memory and CPU interupt Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
IMR .set 0004h ;Interrupt Mask Register
GREG .set 0005h ;Global memory allocation Register
IFR .set 0006h ;Interrupt Flag Register
;System Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PIRQR0 .set 07010h
PIRQR1 .set 07011h
PIRQR2 .set 07012h
PIACKR0 .set 07014h
PIACKR1 .set 07015h
PIACKR2 .set 07016h
SCSR1 .set 07018h ;System Module Control Register
SCSR2 .set 07019h ;System Module Control Register
DINR .set 0701Ch ;System Module Status Register
PIVR .set 0701Eh ;System Interrupt Vector Register
;WD Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
WDCNTR .set 07023h ;WD Counter Register
WDKEY .set 07025h ;WD Key Register
WDCR .set 07029h ;WD Control register
;Serial Peripheral Interface (SPI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SPICCR .set 07040h ;SPI Configuration Control Register
SPICTL .set 07041h ;SPI Operation Control Register
SPISTS .set 07042h ;SPI Status Register
SPIBRR .set 07044h ;SPI Baud Rate Register
SPIEMU .set 07046h ;SPI Emulation buffer Register
SPIRXBUF .set 07047h ;SPI Serial Input Buffer register
SPITXBUF .set 07048h ;SPI Serial Input Buffer register
SPIDAT .set 07049h ;SPI Serial Data Register
SPIPRI .set 0704Fh ;SPI Priority control Register
;Serial Communications Interface (SCI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SCICCR .set 07050h ;SCI Communication Control Register
SCICTL1 .set 07051h ;SCI Control Register 1
SCIHBAUD .set 07052h ;SCI Baud Select register, high bits
SCILBAUD .set 07053h ;SCI Baud Select register, high bits
SCICTL2 .set 07054h ;SCI Control Register 2
SCIRXST .set 07055h ;SCI Receive Status Register
SCIRXEMU .set 07056h ;SCI Emulation data buffer Register
SCIRXBUF .set 07057h ;SCI Receiver data buffer Register
SCITXBUF .set 07059h ;SCI Transmit data buffer Register
SCIPRI .set 0705Fh ;SCI Priority Control register
;External Interrupt Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XINT1CR .set 07070h ;Interrupt 1 Control Register
XINT2CR .set 07071h ;Interrupt 2 Control register
;Digital I/O Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MCRA .set 07090h ;Output Control Reg A
MCRB .set 07092h ;Output Control Reg B
MCRC .set 07094h ;Output Control Reg C
PEDATDIR .set 07095h ;I/O port E Data & Direction reg.
PFDATDIR .set 07096h ;I/O port F Data & Direction reg.
PADATDIR .set 07098h ;I/O port A Data & Direction reg.
PBDATDIR .set 0709Ah ;I/O port B Data & Direction reg.
PCDATDIR .set 0709Ch ;I/O port C Data & Direction reg.
PDDATDIR .set 0709Eh ;I/O port D Data & Direction reg.
;Analog-to-Digital Converter(ADC) registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ADCCTRL1 .set 070A0h ;ADC Control Register 1
ADCCTRL2 .set 070A1h ;ADC Control Register 2
MAXCONV .set 070A2h ;
CHSELSEQ1 .set 070A3h ;
CHSELSEQ2 .set 070A4h ;
CHSELSEQ3 .set 070A5h ;
CHSELSEQ4 .set 070A6h ;
AUTO_SEQ_SR .set 070A7h ;
RESULT0 .set 070A8h ;Result register0
RESULT1 .set 070A9h ;Result register1
RESULT2 .set 070AAh ;Result register2
RESULT3 .set 070ABh ;Result register3
RESULT4 .set 070ACh ;Result register4
RESULT5 .set 070ADh ;Result register5
RESULT6 .set 070AEh ;Result register6
RESULT7 .set 070AFh ;Result register7
RESULT8 .set 070B0h ;Result register8
RESULT9 .set 070B1h ;Result register9
RESULT10 .set 070B2h ;Result register10
RESULT11 .set 070B3h ;Result register11
RESULT12 .set 070B4h ;Result register12
RESULT13 .set 070B5h ;Result register13
RESULT14 .set 070B6h ;Result register14
RESULT15 .set 070B7h ;Result register15
CALIBRATION .set 070B8h ;
;CAN Configuration Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MDER .set 07100h ;
TCR .set 07101h ;
RCR .set 07102h ;
MCR .set 07103h ;
BCR2 .set 07104h ;
BCR1 .set 07105h ;
ESR .set 07106h ;
GSR .set 07107h ;
CEC .set 07108h ;
CAN_IFR .set 07109h ;
CAN_IMR .set 0710Ah ;
LAM0_H .set 0710Bh ; YLP NOTICE
LAM0_L .set 0710Ch ;
LAM1_H .set 0710Dh ;
LAM1_L .set 0710Eh ;
; Message Objects#0
MSGID0L .set 07200h ;
MSGID0H .set 07201h ;
MSGCTRL0 .set 07202h ;
MBX0A .set 07204h ;
MBX0B .set 07205h ;
MBX0C .set 07206h ;
MBX0D .set 07207h ;
; Message Objects#1
MSGID1L .set 07208h ;
MSGID1H .set 07209h ;
MSGCTRL1 .set 0720Ah ;
MBX1A .set 0720Ch ;
MBX1B .set 0720Dh ;
MBX1C .set 0720Eh ;
MBX1D .set 0720Fh ;
; Message Objects#2
MSGID2L .set 07210h ;
MSGID2H .set 07211h ;
MSGCTRL2 .set 07212h ;
MBX2A .set 07214h ;
MBX2B .set 07215h ;
MBX2C .set 07216h ;
MBX2D .set 07217h ;
; Message Objects#3
MSGID3L .set 07218h ;
MSGID3H .set 07219h ;
MSGCTRL3 .set 0721Ah ;
MBX3A .set 0721Ch ;
MBX3B .set 0721Dh ;
MBX3C .set 0721Eh ;
MBX3D .set 0721Fh ;
; Message Objects#4
MSGID4L .set 07220h ;
MSGID4H .set 07221h ;
MSGCTRL4 .set 07222h ;
MBX4A .set 07224h ;
MBX4B .set 07225h ;
MBX4C .set 07226h ;
MBX4D .set 07227h ;
; Message Objects#5
MSGID5L .set 07228h ;
MSGID5H .set 07229h ;
MSGCTRL5 .set 0722Ah ;
MBX5A .set 0722Ch ;
MBX5B .set 0722Dh ;
MBX5C .set 0722Eh ;
MBX5D .set 0722Fh ;
;General Purpose Timer Registers - Event Manager (EVA)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCONA .set 7400h ;General Purpose Timer Control Register
T1CNT .set 7401h ;GP Timer 1 Counter Register
T1CMPR .set 7402h ;GP Timer 1 Compare Register
T1PR .set 7403h ;GP Timer 1 Period Register
T1CON .set 7404h ;GP Timer 1 Control Register
T2CNT .set 7405h ;GP Timer 2 Counter Register
T2CMPR .set 7406h ;GP Timer 2 Compare Register
T2PR .set 7407h ;GP Timer 2 Period Register
T2CON .set 7408h ;GP Timer 2 Control Register
;Full & Simple Compare Unit Registers - Event Manager (EVA)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
COMCONA .set 7411h ;Compare Control register A
ACTRA .set 7413h ;Full Compare Action Control register A
DBTCONA .set 7415h ;Dead-band Timer Control register A
CMPR1 .set 7417h ;Full Compare Unit 1 Compare Register
CMPR2 .set 7418h ;Full Compare Unit 2 Compare Register
CMPR3 .set 7419h ;Full Compare Unit 3 Compare Register
;Capture & QEP Registers - Event Manager (EVA)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CAPCONA .set 7420h ;Capture Control register A
CAPFIFOA .set 7422h ;Capture FIFO Status register A
CAP1FIFO .set 7423h ;Capture 1 Two-level deep FIFO Register
CAP2FIFO .set 7424h ;Capture 2 Two-level deep FIFO Register
CAP3FIFO .set 7425h ;Capture 3 Two-level deep FIFO Register
CAP1FBOT .set 7427h ;
CAP2FBOT .set 7428h ;
CAP3FBOT .set 7429h ;
; Event Manager (EVA) Interrupt Control Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
EVAIMRA .set 742Ch ;EV Interrupt Ma
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