NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8MDQLQCEC
Rev. 1, 10/2018
Ordering Information
See Table 2 on page 6
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
MIMX8MQ7DVAJZAA MIMX8MQ7DVAJZAB
MIMX8MQ6DVAJZAA MIMX8MQ6DVAJZAB
MIMX8MD7DVAJZAA MIMX8MD7DVAJZAB
MIMX8MD6DVAJZAA MIMX8MD6DVAJZAB
MIMX8MQ5DVAJZAA MIMX8MQ5DVAJZAB
Package Information
Plastic Package
FBGA 17 x 17 mm, 0.65 mm pitch
1 i.MX 8M Dual / 8M QuadLite
/ 8M Quad introduction
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors
represent NXP’s latest market of connected streaming
audio/video devices, scanning/imaging devices, and
various devices requiring high-performance, low-power
processors.
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors
feature advanced implementation of a quad Arm
®
Cortex
®
-A53 core, which operates at speeds of up to
1.5 GHz. A general purpose Cortex
®
-M4 core processor
is for low-power processing. The DRAM controller
supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L
memory. There are a number of other interfaces for
connecting peripherals, such as WLAN, Bluetooth, GPS,
displays, and camera sensors. The i.MX 8M Quad and
i.MX 8M Dual processors have hardware acceleration
for video playback up to 4K, and can drive the video
outputs up to 60 fps. Although the i.MX 8M QuadLite
processor does not have hardware acceleration for video
decode, it allows for video playback with software
decoders if needed.
i.MX 8M Dual / 8M
QuadLite / 8M Quad
Applications Processors
Data Sheet for Consumer
Products
1. i.MX 8M Dual / 8M QuadLite / 8M Quad introduction . . . 1
1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Recommended connections for unused interfaces 12
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 13
3.2. Power supplies requirements and restrictions . . . 25
3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 27
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5. I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . 30
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 32
3.7. Output buffer impedance parameters . . . . . . . . . 35
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 37
3.9. External peripheral interface parameters . . . . . . 38
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 74
4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 74
4.2. Boot device interface allocation . . . . . . . . . . . . . . 75
5. Package information and contact assignments . . . . . . . 76
5.1. 17 x 17 mm package information . . . . . . . . . . . . 76
5.2. DDR pin function list for 17 x 17 mm package . . 96
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
