控制模块JTD_CTRL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JTD_CTRL IS
PORT(CLK,CLR:IN STD_LOGIC;
M:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
AT,BT:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END JTD_CTRL;
ARCHITECTURE JTD_1 OF JTD_CTRL IS
SIGNAL Q:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(CLR,CLK,M,AT,BT)
BEGIN
IF CLR='1' THEN Q<="000";
ELSIF(CLK'EVENT AND CLK='1') THEN
IF M="000" THEN Q<="001";
END IF;
IF M="001" THEN Q<="011";
END IF;
IF M="010" THEN Q<="101";
END IF;
IF M="011" THEN Q<="111";
END IF;
IF M>="100" THEN
IF(AT=X"01")OR(BT=X"01") THEN Q<=Q+1;
ELSE Q<=Q;
END IF;
END IF;
END IF;
END PROCESS;
S<=Q;
END JTD_1;
计时模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JTD_TIME IS
PORT(CLK,CLR:IN STD_LOGIC;
M,S:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
AT,BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END JTD_TIME;
ARCHITECTURE JTD_2 OF JTD_TIME IS
SIGNAL ATI,BTI:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ART,AGT,ALT,ABYT:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL BRT,BGT,BLT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
ART<=X"55";
AGT<=X"40";
ALT<=X"15";
ABYT<=X"05";
BRT<=X"65";
BGT<=X"30";
BLT<=X"15";
PROCESS(CLR,CLK,M,S)
BEGIN
IF CLR='1' THEN ATI<=X"01";BTI<=X"01";
ELSIF(CLK'EVENT AND CLK='1') THEN
IF M="000" THEN ATI<=X"01";BTI<=X"51";
END IF;
IF M="001" THEN ATI<=X"01";BTI<=X"06";
END IF;
IF M="010" THEN ATI<=X"41";BTI<=X"01";
END IF;
IF M="100" THEN ATI<=X"06";BTI<=X"01";
END IF;
IF M>="100" THEN
IF(ATI=X"01")OR(BTI=X"01") THEN
CASE S IS
WHEN "000"=>ATI<=ALT;BTI<=BRT;
WHEN "001"=>ATI<=ABYT;
WHEN "010"=>ATI<=AGT;
WHEN "011"=>ATI<=ABYT;
WHEN "100"=>ATI<=ART;BTI<=BLT;
WHEN "101"=>BTI<=ABYT;
WHEN "110"=>BTI<=BGT;
WHEN "111"=>BTI<=ABYT;
WHEN OTHERS=>ATI<=ATI;BTI<=BTI;
END CASE;
END IF;
IF ATI/=X"01" THEN
IF ATI(3 DOWNTO 0)="0000" THEN
ATI(3 DOWNTO 0)<="1001";
ATI(7 DOWNTO 4)<=ATI(7 DOWNTO 4)-1;
ELSE ATI(3 DOWNTO 0)<=ATI(3 DOWNTO 0)-1;
ATI(7 DOWNTO 4)<=ATI(7 DOWNTO 4);
END IF;
END IF;
IF BTI/=X"01" THEN
IF BTI(3 DOWNTO 0)="0000" THEN
BTI(3 DOWNTO 0)<="1001";
BTI(7 DOWNTO 4)<=BTI(7 DOWNTO 4)-1;
ELSE BTI(3 DOWNTO 0)<=BTI(3 DOWNTO 0)-1;
BTI(7 DOWNTO 4)<=BTI(7 DOWNTO 4);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
AT<=ATI;
BT<=BTI;
END JTD_2;
译码模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JTD_LIGHT IS
PORT(CLR:IN STD_LOGIC;
M,S:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
ABL:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END JTD_LIGHT;
ARCHITECTURE JTD_3 OF JTD_LIGHT IS
SIGNAL LT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLR,S,M)
BEGIN
IF CLR='1' THEN LT<=X"00000000";
ELSE IF M="000" THEN LT<="10000001";
END IF;
IF M="001" THEN LT<="00100001";
END IF;
IF M="010" THEN LT<="00011000";
END IF;
IF M="011" THEN LT<="00010010";
END IF;
IF M>="100" THEN
CASE S IS
WHEN "000"=>LT<="00010100";
WHEN "001"=>LT<="10000001";
WHEN "010"=>LT<="01000001";
WHEN "011"=>LT<="00100001";
WHEN "100"=>LT<="01000001";
WHEN "101"=>LT<="00011000";
WHEN "110"=>LT<="00010100";
WHEN "111"=>LT<="00010010";
WHEN OTHERS=>LT<="00010010";
END CASE;
END IF;
END IF;
END PROCESS;
ABL<=LT;
END JTD_3;
显示模块JTD_DIS的设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JTD_DIS IS
PORT(CLK1K,CLK,CLR:IN STD_LOGIC;
M2,M1,M0:IN STD_LOGIC;
AT,BT:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END JTD_DIS;
ARCHITECTURE JTD_4 OF JTD_DIS IS
SIGNAL OU,STL,STH,MM:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DIS,DS:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SL:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
MM<="0"&M2&M1&M0;
STH<=X"A";
PROCESS(CLR,CLK1K)
BEGIN
IF CLR='1' THEN SL<="000";
ELSIF(CLK1K'EVENT AND CLK1K='1')THEN
IF SL="101" THEN SL<="000";
ELSE SL<=SL+1;
END IF;
END IF;
END PROCESS;
PROCESS(SL)
BEGIN
CASE SL IS
WHEN "000"=>OU<=BT(3 DOWNTO 0);
WHEN "001"=>OU<=BT(7 DOWNTO 4);
WHEN "010"=>OU<=AT(3 DOWNTO 0);
WHEN "011"=>OU<=AT(7 DOWNTO 4);
WHEN "100"=>OU<=STL;
WHEN "101"=>OU<=STH;
WHEN OTHERS=>OU<=X"0";
END CASE;
END PROCESS;
PROCESS(OU)
BEGIN
CASE OU IS
WHEN X"0"=>DS<=X"7E";
WHEN X"1"=>DS<=X"30";
WHEN X"2"=>DS<=X"6D";
WHEN X"3"=>DS<=X"79";
WHEN X"4"=>DS<=X"33";
WHEN X"5"=>DS<=X"5B";
WHEN X"6"=>DS<=X"5F";
WHEN X"7"=>DS<=X"70";
WHEN X"8"=>DS<=X"7F";
WHEN X"9"=>DS<=X"7B";
WHEN X"A"=>DS<=X"4F";
WHEN OTHERS=>DS<=X"00";
END CASE;
END PROCESS;
PROCESS(MM,CLK)
BEGIN
IF MM>=X"4" THEN STL<=X"5";
ELSE STL<=MM+1;
END IF;
IF CLR='1' THEN DIS<=X"00";
ELSIF MM>=X"4" THEN DIS<=DS;
ELSIF SL<"100" THEN
IF CLK='0' THEN DIS<=DS;
ELSE DIS<=X"00";
END IF;
ELSE DIS<=DS;
END IF;
END PROCESS;
LED<=DIS(6 DOWNTO 0);
SEL<=SL;
END JTD_4;
分频器JTD_FQU的设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JTD_FQU IS
PORT(CLK1K:IN STD_LOGIC;
CLK:OUT STD_LOGIC);
END JTD_FQU;
ARCHITECTURE JTD_5 OF JTD_FQU IS
SIGNAL Q:STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
PROCESS(CLK1K)
BEGIN
IF(CLK1K'EVENT AND CLK1K='1') THEN Q<=Q+1;
END IF;
END PROCESS;
CLK<=Q(9);
END JTD_5;
