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《GSM信道均衡技术：基于MSC8126的维特比算法解析》 GSM（Global System for Mobile Communications，全球移动通信系统）是一种广泛使用的数字蜂窝通信标准，其核心部分包括了信道编码、调制解调以及信道均衡等关键技术。在GSM系统中，由于无线信道的多径传播和频率选择性衰落，信号质量会受到严重影响，这时就需要采用信道均衡技术来改善接收端的信号质量。本文将重点探讨一种在飞思卡尔的MSC8126维特比协处理器上实现的GSM信道均衡算法——SOVA（Successive Over-Relaxation Viterbi Algorithm，逐步超松弛维特比算法）。维特比算法，由Andrew J. Viterbi在1967年提出，是最大似然序列估计的一种高效算法，广泛应用于数字通信、语音识别等领域。在GSM系统中，它主要用于解码经过卷积编码的信号，通过找到最有可能的路径来恢复原始信息。然而，当信道条件恶劣时，单纯依赖维特比解码可能无法达到理想效果，因此引入了信道均衡技术。 SOVA算法是维特比算法的一种改进形式，它通过引入超松弛策略，增强了在多径传播环境下的性能。在每个迭代步骤中，SOVA不仅更新当前状态的概率，还考虑了前一状态的影响，从而更准确地估计出信道的均衡状态。这一策略提高了算法的收敛速度和解码精度，尤其适用于快速变化的无线信道环境。飞思卡尔的MSC8126是一款专为无线通信设计的高性能数字信号处理器，内置了专门的维特比协处理器，能够高效执行维特比算法及其变种，如SOVA。该芯片的优化架构使得GSM信道均衡在硬件层面得以高效实现，降低了系统的功耗，提升了通信质量。在"MSC8126_gsm viterbi_gsm信道均衡_维特比均衡"的项目中，研究者们将SOVA算法应用于MSC8126，通过实际测试验证了其在GSM信道中的有效性。其中，"gsm.pdf"文档可能包含了详细的设计原理、实现过程以及实验结果分析，对于深入理解GSM信道均衡和维特比算法的结合应用具有重要参考价值。 GSM信道均衡技术，特别是基于SOVA的维特比算法，对于保证GSM通信的稳定性和可靠性至关重要。通过飞思卡尔MSC8126这样的专用处理器，这些高级算法能够在实际系统中得到高效实现，为无线通信领域提供了强大的工具。未来，随着5G和其他新型通信技术的发展，类似的研究将继续推动信道均衡技术的进步，以应对更加复杂多变的通信环境。

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Freescale Semiconductor

Application Note

AN2943

Rev. 0, 5/2005

This application note describes the theory and implementation

of GSM channel equalization and channel decoding algorithms

using the Freescale MSC8126 Viterbi coprocessor (VCOP). It

also examines the theory behind the soft output Viterbi

algorithm (SOVA) assisted by the VCOP. Code examples

illustrate how the VCOP performs channel equalization and the

SOVA algorithm. A set of suggested design practices for VCOP

usage is followed by a discussion of the VCOP driver, which

provides a simple, easy interface to the VCOP. Examples of

driver usage cover GSM equalization, channel decoding, and

SOVA. The source code and the header file for the VCOP driver

are also presented.

CONTENTS

1 Basics of Convolutional Encoding/Decoding .........2

1.1 Viterbi Decoding .....................................................5

1.2 GSM Equalization, Channel Decoding and SOVA 8

1.3 Soft Output Viterbi Algorithm (SOVA) Assist .....10

2 GSM Channel Equalization and Decoding

on VCOP............................................................... 11

3 Recommended Design Practices ...........................15

3.1 VCOP Features .....................................................15

3.2 Interrupts Versus Polling ......................................16

3.3 Buffer Allocation ..................................................17

3.4 Single-Core Operation ..........................................17

3.5 Multi-Core Operation ............................................17

3.6 GSM Channel Equalization ..................................19

3.7 GSM Channel Decoding .......................................20

4 VCOP Driver .........................................................21

4.1 Driver Structs ........................................................21

4.2 Driver Functions ...................................................22

4.3 Driver Header File ................................................29

4.4 Driver Source Code ...............................................37

5 VCOP Code Examples ..........................................38

5.1 VCOP Driver in GSM Equalization

and GSM Decoding Session ................................. 38

5.2 Pre-Equalization Tasks 4 .........................................1

5.3 Driver Functions for Handling SOVA ..................42

5.4 Interrupt Handling .................................................48

5.5 VCOP Interrupt Handlers for Equalization........... 48

6 Local Profiling Unit (LPU) ...................................50

7 References .............................................................50

GSM Channel Equalization,

Decoding, and SOVA on the

MSC8126 Viterbi Coprocessor (VCOP)

By Manoj Bapat, Dov Levenglick, and Odi Dahan

GSM Channel Equalization, Decoding, and SOVA on the MSC8126 Viterbi Coprocessor (VCOP), Rev. 0

2 Freescale Semiconductor

Basics of Convolutional Encoding/Decoding

1 Basics of Convolutional Encoding/Decoding

Convolutional coding is a method of transmitting code words consisting of 1/rate symbols affected by data bits

instead of transmitting the data bits themselves. Since each data bit is used in more than one code word, the

probability of correctly decoding each bit increases. All examples in this document are for an encoder in which

rate = 1/2 (two symbols create a code word) and the constraint length is the length of the shift register, K, = 3.

Figure 1 shows a pictorial view of such an encoder

Figure 1. Convolutional Encoder Diagram

The transmitted bits are mapped from {0, 1} to {1, –1}, respectively. The channel adds noise to the transmitted

signal, which is generally modeled using additive white gaussian noise (AWGN). This discussion references an

example in which the data {1, 0, 0, 1, 1, 0, 0, 0} is transmitted and the last three bits are for flushing the transmitter.

Table 1 lists the expected results.

Another view of an encoder is the view of a finite state machine (FSM). Figure 2 shows the state diagram view of

the encoder.

1. The initial state of the encoder is assumed to be all zeros. When all the data is encoded, the encoder is flushed by

passing K – 1 zeros through it. The code words that result from these zeros are transmitted as well.

Table 1. Transitions of the Encoder

State of the Encoder Input Bit New State of the Encoder Transmitted Code Word (First, Second)

000 1 100 11

100 0 010 10

010 0 001 11

001 1 100 11

100 1 110 01

110 0 011 01

011 0 001 11

001 0 000 00

Input bit

Output

Code Word

First Code Symbol

Second Code Symbol

Basics of Convolutional Encoding/Decoding

GSM Channel Equalization, Decoding, and SOVA on the MSC8126 Viterbi Coprocessor (VCOP), Rev. 0

Freescale Semiconductor 3

Figure 2. Convolutional Encoder, State Diagram View

Table 2 shows the transitions of the states through transmission.

The rightmost column in Table 1 is equal to the rightmost column in Table 2. Although the state diagram provides

all the information needed to follow the transitions of the convolutional encoder in time, this is not an easy task. To

simplify tracking of the encoder transitions, we introduce the tree diagram in

Figure 3. The bold line follows the

transmitted bits (from the example) through the tree.

Table 2. Transitions of the Encoder, State Diagram View

State of the Encoder Input Bit New State of the Encoder Transmitted Code Word (First, Second)

a 1 b 11

b 0 c 10

c 0 a 11

a 1 b 11

b 1 d 01

d 0 c 01

c 0 a 11

a 0 a 00

a = 00

d = 11

b = 10

c = 01

Encoder

State

Code Word Branch

Input Bit 0

Input Bit 1

GSM Channel Equalization, Decoding, and SOVA on the MSC8126 Viterbi Coprocessor (VCOP), Rev. 0

4 Freescale Semiconductor

Basics of Convolutional Encoding/Decoding

Figure 3. Convolutional Encoder, Tree Diagram View

If we were to sum the states and code words around the bold line into a table, this table would be identical to

Table 2. Tracing the transitions on the tree diagram is easy because the size of the block grows linearly while the

size of the tree grows exponentially. Close inspection of the diagram reveals that the tree structure repeats itself at

as the upper and lower half of the structure at t

are equal to the whole structure at t

. These portions of the

diagram are surrounded by a dotted line. Generally, any tree diagram starts repeating itself after K branches. It is

this repetition that the trellis diagram (

Figure 4) uses to provide all the information graphically and succinctly.

Notice that the upper branch from each state represents a transmitted 0, while the lower branch represents a

transmitted 1. As expected, the flow through the trellis diagram results in

Table 2.

00 a

11 b

10 c

01 d

11 a

00 b

01 c

10 d

00 a

11 b

10 c

01 d

11 a

00 b

01 c

10 d

00 a

11 b

10 c

01 d

11 a

00 b

01 c

10 d

00 a

11 b

10 c

01 d

11 a

00 b

01 c

10 d

00 a

11 b

10 c

01 d

00 a

11 b

t1 t2 t4 t5t3

Code Word Branch

00 a

11 b

10 c

01 d

11 a

00 b

01 c

10 d

00 a

11 b

10 c

01 d

11 a

00 b

01 c

10 d

00 a

11 b

10 c

01 d

11 a

00 b

01 c

10 d

Basics of Convolutional Encoding/Decoding

GSM Channel Equalization, Decoding, and SOVA on the MSC8126 Viterbi Coprocessor (VCOP), Rev. 0

Freescale Semiconductor 5

Figure 4. Convolutional Encoder, Trellis Diagram View

1.1 Viterbi Decoding

To decode the received data, we must maximize the likelihood function of the received sequence (Z) given all

possible transmitted sequences (U

(m)

). P(Z|U

(M’)

) = max P(Z|U

(m)

) over all U

(m)

. The complexity of calculating

the probability and therefore the computational load grows as the length of the received data grows, much as the

complexity increases when we trace the received data using the tree diagram (

Figure 3). To address this problem,

Viterbi devised and proved an algorithm to detach the size of the received data from the complexity of calculation.

The maximum likelihood function is calculated on each received code word rather than on the whole bulk of

received data. The Viterbi algorithm calculates the similarity (distance) of the received symbol at time t

and all

branches entering all states at that time. This distance is the branch metric. Following are ways to calculate the

branch metrics when the inputs are soft symbols.

• Euclidean distance. The Euclidean method involves straightforward distance calculations. The basis

for calculating the distance is the 8-bit, twos complement representation of the maximum values. A

received 0 is represented as 127 and a received 1 is represented as –127. Assuming that the received

code words are {x, y} and we are calculating the distance from state b to state d {0, 1}, the distance is

calculated as shown in

Equation 1:

Equation 1

• Manhattan distance. The Manhattan metric calculates the multiplication of the expected data in the

state and the received data. Assuming we are calculating the BM from state b to state c {0, 1} =

{1, –1} and the received data is {x, y}, as shown in Equation 2:

Equation 2

The Euclidean distance has proven to be mathematically optimal, but it is extremely difficult to implement in

hardware. Although the Manhattan metric is not as mathematically powerful, it has proven to be effective and is

easy to implement in hardware. Therefore, the VCOP uses the Manhattan metric, as do many other Viterbi

coprocessors on the market.

a=00

b=10

c=01

d=11

Input Bit 0

Input Bit 1

t1 t2 t4 t5t3 t6

10 10 10 1010

10 10 10 10 10

01 01 01 01 01

11 11 11 11 11 11

00 00 00 00 00 00

01 01 01 01 01

t7 t9t8

Expected Code Word

Euc

127 x–()

127–()y–()

–=

Man

1 x

⋅()

1–

()

⋅()

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