● Counter using a Conversion Function
● Generated Binary Up Counter
● Counter using Multiple Wait Statements
● Synchronous Down Counter with Parallel Load
● Mod-16 Counter using JK Flip-flops
● Pseudo Random Bit Sequence Generator
● Universal Counter/Register
● n-Bit Synchronous Counter
Shift Registers
● Universal Shift Register/Counter
● TTL164 Shift Register
● Behavioural description of an 8-bit Shift Register
● Structural Description of an 8-bit Shift Register
Memory
● ROM-based Waveform Generator
● A First-in First-out Memory
● Behavioural model of a 16-word, 8-bit Random Access Memory
● Behavioural model of a 256-word, 8-bit Read Only Memory
State Machines
● Classic 2-Process State Machine and Test Bench
● State Machine using Variable
● State Machine with Asynchronous Reset
● Pattern Detector FSM with Test Bench
● State Machine with Moore and Mealy outputs
● Moore State Machine with Explicit State encoding
● Mealy State Machine with Registered Outputs
● Moore State Machine with Concurrent Output Logic
Systems
● Pelican Crossing Controller
● Simple Microprocessor System
● Booth Multiplier
● Lottery Number Generator
● Digital Delay Unit
● Chess Clock
ADC and DAC
● Package defining a Basic Analogue type
● 16-bit Analogue to Digital Converter
● 16-bit Digital to Analogue Converter
● 8-bit Analogue to Digital Converter
● 8-bit Unipolar Successive Approximation ADC
http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (2 of 67) [23/1/2002 4:15:07 ]
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