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AVR Bootloader是一种在AVR微控制器中实现的软件组件，允许通过串行通信接口（如UART或USB）对程序存储器进行非侵入式的更新。这个“AVR_bootleader.rar”压缩包提供了关于AVR单片机自编程和引导区操作的详细资料，主要包含一个名为“AVR_bootleader.PDF”的文档。在AVR微控制器中，自编程功能是指微控制器能够读取并写入自己的程序存储器，通常用于更新固件或修复错误的代码。这种特性对于开发过程以及远程维护设备的固件升级非常重要。引导区是程序存储器的一部分，它在上电时首先被加载到CPU，并执行初始化任务，包括检查新的固件版本、校验数据完整性，以及将新代码安全地写入主程序存储区。 AVR Bootloader的工作流程通常包括以下几个步骤： 1. **启动过程**：当AVR单片机上电或复位时，会从引导区加载代码并执行。 2. **通信协议**：Bootloader使用特定的通信协议（如USART或SPI）与主机（如PC或另一个微控制器）建立连接。 3. **固件传输**：主机通过通信接口向Bootloader发送新的固件二进制文件。 4. **校验与存储**：Bootloader接收并校验新固件的完整性和正确性，然后将其存储到程序存储器的适当位置。 5. **跳转到应用**：一旦新固件被确认无误，Bootloader会跳转到主应用程序的入口点，执行新固件。在“AVR_bootleader.PDF”文档中，可能涵盖了以下内容： 1. **Bootloader结构**：包括引导区的大小、布局，以及Bootloader的代码组织。 2. **编程算法**：如使用ISP（In-System Programming）或PDI（Parallel Data Input）接口进行编程的详细步骤。 3. **通信协议详解**：例如如何使用USART（通用同步/异步收发传输器）或USB进行数据传输。 4. **固件更新流程**：从连接建立到固件写入的完整过程。 5. **错误处理**：在固件传输和验证过程中可能出现的问题及其解决方案。 6. **安全机制**：防止非法固件更新的保护措施，如密码验证或数字签名。 7. **实例应用**：可能包括实际项目中的Bootloader实现案例，演示如何在具体项目中使用和定制Bootloader。了解并掌握这些知识对于AVR单片机的开发者来说至关重要，因为它不仅简化了开发过程，还使得远程固件更新成为可能，从而增强了系统的可维护性和灵活性。通过深入研究“AVR_bootleader.PDF”，你可以更全面地理解和应用AVR单片机的自编程技术。

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AVR_bootleader.rar （1个子文件）

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AVR109: Self-programming

Features

• AVR109 Code Fits in All AVR

Microcontrollers with Boot Block

• Read and Write Both Flash and EEPROM Memories

• Uses the AVRProg Protocol

• Read and Write Lock Bits

Introduction

This application note describes how an AVR with the Store Program Memory (SPM)

instruction can be configured for Self-programming. The AVR communicates via the

UART with a PC running the AVRprog programming software. This enables Flash and

EEPROM programming without the need for an external programmer.

A Boot Loader program is placed inside the Boot Section of the Flash memory. This

program handles communication with the host PC, and facilitates programming of

both Flash and EEPROM. Once programmed, different levels of protection can be

individually applied to both the boot and application portion of the Flash memory. The

AVR thus offers a unique flexibility, allowing the user extensive degrees of memory

protection.

SPM Explained

To get a better understanding of the AVRs’ self-programming capabilities, the basics

of this feature are explained below.

Memory Organization

The Flash memory is divided into two sections, one Application section and one Boot

Loader section. The Application section contains the main code for the application,

while the Boot Loader section contains the code for the actual Self-programming. The

SPM instruction can only be executed from the Boot Loader section. (Note: The Boot

Loader section can also be used for ordinary application code.)

The Flash memory is divided into pages containing 32, 64, or 128 words each. The

usage of pages is explained later. The entire memory span, both Application and Boot

Loader sections, is divided into pages. For instance, a device with 8 kbytes of Flash

and page size of 32 words (64 bytes) will therefore have a total of 128 pages. The

memory organization is shown in Figure 1.

8-bit

RISC

Microcontroller

Application

Note

Rev. 1644C–AVR–08/02

存储器组织

AVR109

1644C–AVR–08/02

Figure 1. Memory Organization

The size of the Boot Loader section can be selected using the two BOOTSZx Fuses.

The fuses select one of four predefined sizes. The BOOTSZx Fuses can be changed

using Serial or Parallel Programming. Refer to the devices' data sheet for details.

If a Boot Loader is implemented, it can be called either directly from the Application code

using calls or jumps, or by programming the BOOTRST Fuse. When the BOOTRST

Fuse is programmed, the CPU will start execution in the Boot Loader section on Reset,

instead of starting at address 0. The BOOTRST Fuse can be changed using Serial or

Parallel Programming.

Read-While-Write

Capabilities

In addition to the selectable division between the application and Boot Loader sections,

the Flash is also divided into two fixed-size sections. The first section is the Read-While-

Write (RWW) section. The second is the No-Read-While-Write (NRWW) section. The

NRWW section size always equals the largest selectable Boot Loader section size, thus

the Boot Loader section occupies all or part of the NRWW section. This is illustrated in

Figure 2.

Figure 2. RWW and NRWW Sections

The difference between the sections is that the NRWW section is accessible while

updating the RWW section. It is not possible to access the RWW section when it’s being

updated. When the NRWW is updated (e.g., updating the Boot Loader code itself), the

Application Section

Boot Loader Section

Flash Memory

Page 13

Page 14

Page 15

Page 16

32, 64 or 128

Words

RWW Section

NRWW Section

Flash Memory

Boot Loader Alternatives

AVR109

1644C–AVR–08/02

CPU is halted during the whole operation. In other words, No-Read-While-Writing to the

NRWW section, but possible to Read-While-Writing to the RWW section. Refer to the

devices’ data sheet for details.

This functionality makes it possible to continue execution of critical code while updating

the RWW section. Note that this critical code must be contained within the NRWW sec-

tion (not necessarily in the Boot Loader section). See the section on interrupts below for

more information.

The ATmega163 and ATmega323 devices don’t have NRWW and RWW sections, only

the selectable division into application and Boot Loader sections. Any updates to Flash

memory on these devices halt the CPU during the whole operation.

Using the SPM

Instruction

All Self-programming operations are performed using the SPM instruction. The opera-

tion is selected using the SPMCR Register. The register is organized as shown in Figure

Figure 3. The SPMCR Register

When using the SPM function, the SPMEN bit must always be set within four cycles

prior to executing the SPM instruction. This is to prevent unintentional Flash updates.

The software must ensure that no interrupt routines are called between setting the

SPMEN bit and executing the SPM instruction, thus exceeding the 4-cycle limit. The

other four highlighted bits choose between the different SPM functions. The SPMEN bit

is automatically cleared together with the function bit when the operation is completed.

The SPM functions are described below.

Page Erase All Flash memory updates are done page by page. Before writing new data to a page,

the page must be erased.

The Z-register is used to select the page to be erased. Set up the Z-register to point to a

byte in the page to be erased. The lower bits selecting the byte within the page are

ignored. For instance, on a device with a page size of 32 words (64 bytes), the lower six

bits of the Z-register are ignored.

To erase a page, set the PGERS and SPMEN bits in the SPMCR Register and execute

the SPM instruction.

SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN

Bit 0Bit 7

SPM寄存器

AVR109

1644C–AVR–08/02

Loading Page Buffer To write new data to a page, the Page Buffer must be filled first. The Page Buffer is a

separate (not SRAM) write-only buffer holding one temporary page. This buffer must be

filled word by word. The buffer is copied to Flash memory in one operation.

The Z-register is used to select the word to be written into the buffer. The LSB of Z is

ignored, as an entire word is always written in one operation. Single byte access is thus

not possible. The higher bits of Z selecting the page are ignored when writing to the

Page Buffers. The Z-register bit structure for a 32-word (64-byte) page is shown in Fig-

ure 4. Larger page sizes use more bits for word selection.

Figure 4. Writing to Page Buffer

To write a word to the Page Buffer, load the word into the R1:R0 Registers. Set the Z-

The SPM instruction must then be executed within four cycles.

Page Write When the Page Buffer is loaded with new data, it must be written to Flash memory. To

do this, set up the Z-register the same way as described in the section regarding Page

Erase. Then set the PGERS and SPMEN bits in the SPMCR Register and execute the

SPM instruction within four cycles. The R1:R0 Register contents are ignored. The use of

the Z-register for 32-word (64-byte) page write is shown in Figure 5.

Figure 5. Writing a Page to Flash

32-word Page Buffer

Bit 0

Word Select

Bit 1

Bit 5

Bit 6

Page 45

Page 46

Page 47

Flash Memory

32-word Page Buffer

Bit 0

Page Select

Bit 1

it 5

Bit 6

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