�
Saturday, March 6, 2010
VHDL code for BCD to 7-segment display converter
Here is a program for BCD to 7-segment display decoder. The module takes 4 bit BCD as
input and outputs 7 bit decoded output for driving the display unit.A seven segment display
can be used to display decimal digits.They have LED or LCD elements which becomes active
when the input is zero.The figure shows how different digits are displayed:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'