uart.rar_uart 测试_verilog代码测试

Release 13.4 - par O.87xd (nt) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. Fri Dec 14 16:58:58 2012 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: 1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. 2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. 3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator. INPUT FILE: top_map.ncd OUTPUT FILE: top_pad.txt PART TYPE: xc3s1600e SPEED GRADE: -4 PACKAGE: fg320 Pinout by Pin Number: +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |A1 | | |GND | | | | | | | | | | | | |A2 | | |TDI | | | | | | | | | | | | |A3 | |IBUF |IP |UNUSED | |0 | | | | | | | | | |A4 | |DIFFM |IO_L24P_0 |UNUSED | |0 | | | | | | | | | |A5 | |DIFFMI |IP_L22P_0 |UNUSED | |0 | | | | | | | | | |A6 | |DIFFS |IO_L20N_0 |UNUSED | |0 | | | | | | | | | |A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |A8 | |IOB |IO |UNUSED | |0 | | | | | | | | | |A9 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |A10 | |DIFFS |IO_L12N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |A11 | |IOB |IO |UNUSED | |0 | | | | | | | | | |A12 | |DIFFM |IO |UNUSED | |0 | | | | | | | | | |A13 |sys_clk |IBUF |IO_L05P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | |A14 | |DIFFS |IO_L04N_0 |UNUSED | |0 | | | | | | | | | |A15 | |DIFFSI |IP_L02N_0 |UNUSED | |0 | | | | | | | | | |A16 | |DIFFS |IO_L01N_0 |UNUSED | |0 | | | | | | | | | |A17 | | |TCK | | | | | | | | | | | | |A18 | | |GND | | | | | | | | | | | | |B1 | | |PROG_B | | | | | | | | | | | | |B2 | | |GND | | | | | | | | | | | | |B3 | |DIFFS |IO_L25N_0/HSWAP |UNUSED | |0 | | | | | | | | | |B4 | |DIFFS |IO_L24N_0 |UNUSED | |0 | | | | | | | | | |B5 | |DIFFSI |IP_L22N_0 |UNUSED | |0 | | | | | | | | | |B6 | |DIFFM |IO_L20P_0 |UNUSED | |0 | | | | | | | | | |B7 | | |VCCAUX | | | | | | | |2.5 | | | | |B8 | |DIFFMI |IP_L13P_0/GCLK8 |UNUSED | |0 | | | | | | | | | |B9 | |DIFFSI |IP_L13N_0/GCLK9 |UNUSED | |0 | | | | | | | | | |B10 | |DIFFM |IO_L12P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |B11 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | |B12 | | |VCCAUX | | | | | | | |2.5 | | | | |B13 | |DIFFS |IO_L05N_0/VREF_0 |UNUSED | |0 | | | | | | | | | |B14 |tx |IOB |IO_L04P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |B15 | |DIFFMI |IP_L02P_0 |UNUSED | |0 | | | | | | | | | |B16 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | |B17 |