<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Thu Sep 06 13:38:03 2018">
<section name="Project Information" visible="false">
<property name="ProjectID" value="a02d7b3354a8408d88b31062cd02de3f" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Other">
<property name="GuiMode" value="130" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="119" type="TclMode"/>
</item>
</section>
</application>
</document>
uart_top.rar （8个子文件） 
uart_top uart_top.ip_user_files ipstatic uart_top.srcs sources_1 new 
uart_rx.v 3KB speed_select.v 2KB uart_tx.v 3KB uart_top.v 2KB uart_top.hw uart_top.lpr 290B uart_top.sim uart_top.xpr 6KB uart_top.cache wt webtalk_pa.xml 1KB project.wpc 61B资源评论
