module fft_r4_256p(clk, reset, start, ce, din_real, din_imag,
exp_in, blk_exp, dout_real, dout_imag, done, valid);
parameter data_width = 18; // input data width;
parameter twid_width = 16; // twiddle factor data width;
parameter addrwidth = 8 ;
input clk, reset, start, ce;
input signed [data_width - 1:0] din_real, din_imag;
input wire [4:0] exp_in;
output reg done, valid;
output wire [4:0] blk_exp;
output reg signed [data_width - 1:0] dout_real;
output reg signed [data_width - 1:0] dout_imag;
wire ce1, ce2, ce3, ce4, ce5, ce6, ce7, ce8, ce9;
wire start1, start2, start3, start4, start5, start6, start7, start8, start9;
wire [4:0] exp0, exp1, exp2, exp3;
wire [1:0] state0, state1, state2, state3;
wire signed [data_width - 1:0] real0, real1, real2, real3, real4;
wire signed [data_width - 1:0] imag0, imag1, imag2, imag3, imag4;
wire signed [data_width + 1:0] r0, i0;
wire signed [data_width + 2:0] r1, r2, r3;
wire signed [data_width + 2:0] i1, i2, i3;
wire signed [twid_width - 1:0] wr1, wr2, wr3;
wire signed [twid_width - 1:0] wi1, wi2, wi3;
always @(posedge clk)
begin
// blk_exp <= exp3;
dout_real <= real4;
dout_imag <= imag4;
done <= start9;
valid <= ce9;
end
delay_line #(1,5) U6 (.clk(clk), .din(exp3), .dout(blk_exp));
ctrl_stage0 #(data_width,addrwidth) U_stage0(.clk(clk),
.reset(reset),
.start(start),
.ce(ce),
.din_real(din_real),
.din_imag(din_imag),
.nextce(ce1),
.nextstart(start1),
.dout_real(real0),
.dout_imag(imag0));
butfly0 #(data_width) U_butfly0(.clk(clk),
.start(start1),
.ce(ce1),
.dr(real0),
.di(imag0),
.exp_in(exp_in),
.exp_out(exp0),
.state(state0),
.Re(r0),
.Im(i0),
.nextce(ce2),
.nextstart(start2));
ctrl_stage1 #(data_width + 2,addrwidth) U_stage1(.clk(clk),
.reset(reset),
.start(start2),
.ce(ce2),
.blk_st(state0),
.din_real(r0),
.din_imag(i0),
.nextce(ce3),
.nextstart(start3),
.dout_real(real1),
.dout_imag(imag1));
twidgen1 #(twid_width) U_twid1 (.clk(clk), .ce(ce3), .wr(wr1), .wi(wi1));
butflyr4 #(data_width,twid_width) U_butfly1(.clk(clk),
.start(start3),
.ce(ce3),
.dr(real1),
.di(imag1),
.exp_in(exp0),
.wr(wr1),
.wi(wi1),
.exp_out(exp1),
.state(state1),
.Re(r1),
.Im(i1),
.nextce(ce4),
.nextstart(start4));
ctrl_stage2 #(data_width + 3,addrwidth) U_stage2(.clk(clk),
.reset(reset),
.start(start4),
.ce(ce4),
.blk_st(state1),
.din_real(r1),
.din_imag(i1),
.nextce(ce5),
.nextstart(start5),
.dout_real(real2),
.dout_imag(imag2));
twidgen2 #(twid_width) U_twid2 (.clk(clk), .ce(ce5), .wr(wr2), .wi(wi2));
butflyr4 #(data_width,twid_width) U_butfly2(.clk(clk),
.start(start5),
.ce(ce5),
.dr(real2),
.di(imag2),
.exp_in(exp1),
.wr(wr2),
.wi(wi2),
.exp_out(exp2),
.state(state2),
.Re(r2),
.Im(i2),
.nextce(ce6),
.nextstart(start6));
ctrl_stage3 #(data_width + 3,addrwidth) U_stage3(.clk(clk),
.reset(reset),
.start(start6),
.ce(ce6),
.blk_st(state2),
.din_real(r2),
.din_imag(i2),
.nextce(ce7),
.nextstart(start7),
.dout_real(real3),
.dout_imag(imag3));
twidgen3 #(twid_width) U_twid3 (.clk(clk), .ce(ce7), .wr(wr3), .wi(wi3));
butflyr4 #(data_width,twid_width) U_butfly3(.clk(clk),
.start(start7),
.ce(ce7),
.dr(real3),
.di(imag3),
.exp_in(exp2),
.wr(wr3),
.wi(wi3),
.exp_out(exp3),
.state(state3),
.Re(r3),
.Im(i3),
.nextce(ce8),
.nextstart(start8));
ctrl_stage4 #(data_width + 3,addrwidth) U_stage4(.clk(clk),
.reset(reset),
.start(start8),
.ce(ce8),
.blk_st(state3),
.din_real(r3),
.din_imag(i3),
.nextce(ce9),
.nextstart(start9),
.dout_real(real4),
.dout_imag(imag4));
endmodule