IP175G
Data Sheet
1 / 67
July 06, 2012
Copyright © 2012, IC Plus Corp. IP175G-DS-R00
5 Port 10/100 Ethernet Integrated Switch
(85nm /Extreme Low Power, PWMT
®
and AFT
®
)
Features General Description
z 5 port Embedded 10/100 PHY Switch Controller
z Support 5 100BaseTX or 4 100Base TX + 1 FX
z 10M PHY only support 10BaseTe
z Support Auto MDI-MDIX function
z Power Management Tool (PWMT®)
- APS, auto-power saving while Link-off
- IEEE 802.3az protocol based power saving
- WOL+®, light traffic power saving
- PWD, force-off power saving
z Support Auto Factory Test (AFT®)
z Single Power 3.3V supply
z Built in 1.1V core voltage LDO Regulator
z Two Priority queues per port
z Support 802.1p & DiffServ based QoS
z QoS
- Port base
- 802.1p
- IP DiffServ IPV4/IPV6
- TCP/UDP port number
- Pins configure ports priority (VIP port)
z Support max forwarding packet length
1552/1536 bytes option
z Support port mirror function
z Support 1k MAC address
z Support broadcast storm protection
z Support port trunking (LACP)
z Support 16 VLAN (IEEE Std 802.1q)
- Port-based/Tagged-based VLAN
- Support insert, remove tag
z Built-in 50 ohm resistors for simplifying BOM
z 85nm Process
z Package and operation temperature
- IP175G: 48 Pin(6mmx6mm) QFN, 0~70℃
- IP175GI: 48 Pin(6mmx6mm) QFN, -40~85℃
IP175G is fabricated with advanced CMOS
(85nm) technology and only requires a 3.3V sinlge
power supply. This feature makes IP175G used
very low power consume, such as the full load
operation (100Mbps full duplex 5 ports), it only
takes 0.45w.
IP175G also supports Power Management Tool
(PWMT
®) for IEEE 802.3az, APS, WOL+ and PWD
for Green Power. While two link devices have no
IEEE 802.3az capability, IP175G use WOL+ to
change link from 100Mbps to 10Mbps for saving
power.
The PWD of IP175G is designed for power
down switch immediately by pushing a botton, user
don’t plug out the power adapter. Push the botton
again, it will power on immediately.
Except Low Power and Rich Power Saving
method, IP175G supports AFT
® for saving
Customer Testing Cost. By using a push bottom
and cables, IP175G will Auto test completely by
itself.
IP175G/IP175GI are available in 48 QFN lead
free package.
Application
5 port 10/100 Dumb swith
4TX+1FX Dumb Switcn
IP175G
Data Sheet
2 / 67
July 06, 2012
Copyright © 2012, IC Plus Corp. IP175G-DS-R00
Table of Contents
Features..................................................................................................................................................................................1
General Description...............................................................................................................................................................1
Table of Contents...................................................................................................................................................................2
List of Tables...........................................................................................................................................................................4
List of Figures.........................................................................................................................................................................5
Revision History.....................................................................................................................................................................6
1 Pin diagram....................................................................................................................................................................7
1.1 IP175G Pin diagram (QFN48).................................................................................................. 7
2 IP175G application diagram ........................................................................................................................................8
2.1 An 5 TP port switch application................................................................................................ 8
2.2 An 5-port switch mixed with a fiber port................................................................................... 8
3 Pin description...............................................................................................................................................................9
3.1 Analog pins .............................................................................................................................. 9
3.2 MDI (Media Dependent Interface)............................................................................................ 9
3.3 System clock & reset pins...................................................................................................... 10
3.4 Boundry scan & test mode..................................................................................................... 10
3.5 EEPROM interface /SMI (Serial Management interface)........................................................11
3.6 Miscellaneous setting pins ..................................................................................................... 12
3.7 LED interface ......................................................................................................................... 13
3.8 Power & ground pads............................................................................................................. 13
4 Functional Description................................................................................................................................................14
4.1 Switch Engine and Queue Management ............................................................................... 14
4.1.1 Switch Engine .............................................................................................................. 14
4.1.2 Packet Forwarding....................................................................................................... 14
4.1.3 Flow control.................................................................................................................. 14
4.1.4 Backpressure ............................................................................................................... 14
4.1.5 Broadcast storm protection.......................................................................................... 14
4.2 Rserved Group MAC Address................................................................................................ 15
4.3 Green Power .......................................................................................................................... 16
4.3.1 Auto Power Saving Mode ............................................................................................ 16
4.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) ............................................................ 16
4.3.3 WOL+ (Wake On LAN Plus) ........................................................................................ 16
4.4 Force Power Off ..................................................................................................................... 17
4.5 Auto Factory Test (AFT) Mode............................................................................................... 18
4.6 Reset...................................................................................................................................... 18
4.7 Serial management interface ................................................................................................. 19
System diagram...................................................................................................................................................................19
4.8 CoS ........................................................................................................................................ 20
4.8.1 Port base priority.......................................................................................................... 20
4.8.2 Frame base priority ...................................................................................................... 20
4.8.2.1 VLAN tag and TCP/IP TOS................................................................................ 20
4.8.2.2 IPv4/IPv6 DiffServ.............................................................................................. 21
4.8.2.3 TCP/UDP logical port priority............................................................................. 22
4.9 Port Mirroring ......................................................................................................................... 22
4.10 Link Aggergation .................................................................................................................... 23
4.11 Buffer Aging............................................................................................................................ 25
4.12 PAD Driving Calibration.......................................................................................................... 25
4.13 Fiber port configuration .......................................................................................................... 25
5 Register descriptions ..................................................................................................................................................26
5.1 Register map.......................................................................................................................... 26
5.1.1 MII register map ........................................................................................................... 26
6 PHY registers ..............................................................................................................................................................27
6.1 MII Register............................................................................................................................ 28
IP175G
Data Sheet
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July 06, 2012
Copyright © 2012, IC Plus Corp. IP175G-DS-R00
6.2
MMD Control Register............................................................................................................ 35
6.3 MMD Data Register................................................................................................................ 35
6.4 LED mode Control Register ................................................................................................... 39
6.5 Register Page mode Control Register ................................................................................... 40
6.6 WOL+ Control Register.......................................................................................................... 40
6.7 Switch control registers (I)...................................................................................................... 42
6.8 Test mode control registers.................................................................................................... 43
6.9 Port mirroring control registers............................................................................................... 44
6.10 Debug Register ...................................................................................................................... 44
6.11 Fiber duplex setting registers................................................................................................. 45
6.12 Backpressure setting registers............................................................................................... 46
6.13 TCP/UDP port priority registers.............................................................................................. 46
6.14 Test mode............................................................................................................................... 47
6.15 CoS control registers – port 0 ................................................................................................ 47
6.16 CoS control registers – port 1 ................................................................................................ 47
6.17 CoS control registers – port 2 ................................................................................................ 47
6.18 CoS control registers – port 3 ................................................................................................ 48
6.19 CoS control registers – port 4 ................................................................................................ 48
6.20 Switch control registers (IV) ................................................................................................... 48
6.21 Reserved Group MAC addresses .......................................................................................... 50
6.22 Switch control registers (II)..................................................................................................... 54
6.23 EEE Timing Parameter........................................................................................................... 55
6.24 WOL (Wake on LAN).............................................................................................................. 56
6.25 Link Aggregation .................................................................................................................... 56
6.26 VLAN Group Control Register................................................................................................ 57
6.26.1 VLAN Classification ..................................................................................................... 57
6.26.2 VLAN Ingress Rule ...................................................................................................... 57
6.26.3 Default VLAN Information ............................................................................................ 58
6.26.4 VLAN TAG Control Register ........................................................................................ 58
6.26.5 Port Based VLAN Member Register ............................................................................ 59
6.26.6 Leaky VLAN Control Register...................................................................................... 59
6.27 VLAN Table ............................................................................................................................ 59
6.27.1 VLAN Control Register................................................................................................. 59
6.27.2 VLAN Identifier Register .............................................................................................. 59
6.27.3 VLAN Member Register............................................................................................... 60
7 Electrical Characteristics ............................................................................................................................................62
7.1 Absolute Maximum Rating ..................................................................................................... 62
7.2 DC Characteristic ................................................................................................................... 62
7.3 AC Timing............................................................................................................................... 63
7.3.1 Power On Sequence and Reset Timing....................................................................... 63
8 Crystal Specifications..................................................................................................................................................63
8.1.1 EEPROM Timing.......................................................................................................... 65
8.1.1.1 Data read cycle.................................................................................................. 65
8.1.1.2 Command cycle ................................................................................................. 65
8.2 Thermal Data.......................................................................................................................... 65
9 Order Information........................................................................................................................................................66
10 Package Detail ............................................................................................................................................................67
10.1 48 QFN Outline Dimensions .................................................................................................. 67
IP175G
Data Sheet
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July 06, 2012
Copyright © 2012, IC Plus Corp. IP175G-DS-R00
List of Tables
Table 1 Pin description................................................................................................................9
Table 2 Rserved Group M
AC Address table.............................................................................15
Table 3 TCP/UDP logical port priority t
able ..............................................................................22
Table 4 Fiber port Parameter
....................................................................................................25
Table 5 MII regis
ter map table ..................................................................................................26
Table 6 PHY Regis
ter Map .......................................................................................................27
Table 7 MMD Control Regis
ter table.........................................................................................35
Table 8 MMD Data Register t
able.............................................................................................35
Table 9 LED mode Control Register t
able ................................................................................39
Table 10 Register Page mode Control
Register table ..............................................................40
Table 11 WOL+ Control Regis
ter table .....................................................................................40
Table 12 Switch control regis
ters (I) table.................................................................................42
Table 13 Test mode control regi
sters table...............................................................................43
Table 14 Port mirroring control regis
ters table..........................................................................44
Table 15 Debug Regi
ster table .................................................................................................44
Table 16 Fiber duplex s
etting registers table............................................................................45
IP175G
Data Sheet
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July 06, 2012
Copyright © 2012, IC Plus Corp. IP175G-DS-R00
List of Figures
Figure 1 Pin Diagram ................................................................................................................. 7
Figure 2 Application Diagram
..................................................................................................... 8
Figure 3 WOL+ Application Diagram
........................................................................................ 16
Figure 4 Magic Pack
et Format ................................................................................................. 17
Figure 5 Force Power Off Applic
ation Diagram........................................................................ 17
Figure 6 Auto Factory Tes
t Application Diagram...................................................................... 18
Figure 7 Serial management interface Read / W
rite Diagram ................................................. 19
Figure 8 VLAN tag and T
CP/IP TOS frame.............................................................................. 20
Figure 9 IPv4/IPv6 Dif
fServ frame............................................................................................ 21
Figure 10 Port Mirroring Sec
urity Block Diagram..................................................................... 23
Figure 11 Trunk Channel Behavior Block Diagram
.................................................................. 23
Figure 12 Load Balance Block Diagram
................................................................................... 24
Figure 13 Fiber FXSD applic
ation circuit.................................................................................. 25
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