RF01 Datasheet
3
○
c
BlueX Microelectronics Confidential. All Rights Reserved.
7.11 Control for clk_src_uart1 ............................................................................... 52
7.12 Control for clk_src_pwm ............................................................................... 53
7.13 Control for clock gate(AWO power domain) ................................................. 54
7.14 Control for clock gate(CPU power domain) ................................................... 57
7.15 Control for clock gate(PER power domain) ................................................... 59
8 Reset system ............................................................................................................. 63
8.1 General description .................................................................................................. 63
8.2 Reset system of AWO power domain ....................................................................... 66
8.3 Reset system of CPU power domain ........................................................................ 69
8.4 Reset system of PER power domain ......................................................................... 70
8.5 Table for system clock and reset .............................................................................. 73
9 IO Mux ...................................................................................................................... 78
10 PMU .......................................................................................................................... 84
10.1 Power supply diagram ................................................................................... 84
10.2 PMU FSM ....................................................................................................... 85
10.3 PMU mode1................................................................................................... 86
10.4 PMU mode2................................................................................................... 87
10.5 PMU mode3................................................................................................... 88
IO status retention function.................................................................. 89
SRAM retention function ...................................................................... 90
Switching voltage of CPU/BLE/PER power domain ............................... 91
CPU register retention function ............................................................ 91
Programming flow ................................................................................ 91
10.6 Clock and reset .............................................................................................. 92
11 CPU ........................................................................................................................... 93
11.1 General description ....................................................................................... 93
11.2 Feature list ..................................................................................................... 94
11.3 NVIC ............................................................................................................... 94
11.4 Memory protection unit ................................................................................ 95
11.5 Clock and reset .............................................................................................. 95
12 System interrupt ....................................................................................................... 96
12.1 BLE sleep timer interrupt .............................................................................. 96
12.2 External interrupt .......................................................................................... 97
12.3 Software interrupt ......................................................................................... 99
