################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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TM7705 fpga verilog.rar (688个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
TM7705_top.bit 3.86MB
waveform.csv 44KB
xsim.dbg 1KB
TM7705_top_routed.dcp 3MB
TM7705_top_placed.dcp 2.56MB
TM7705_top_opt.dcp 1.79MB
ila_0.dcp 1.43MB
ila_0.dcp 1.09MB
ila_0.dcp 1.09MB
ila_0.dcp 1.09MB
ila_0.dcp 1.08MB
ila_0.dcp 1.07MB
ila_0.dcp 1.05MB
ila_0.dcp 1.05MB
ila_0.dcp 978KB
ila_0.dcp 845KB
ila_0.dcp 842KB
ila_0.dcp 677KB
ila_0.dcp 644KB
ila_0.dcp 634KB
ila_0.dcp 621KB
dbg_hub.dcp 347KB
TM7705_top.dcp 53KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
waveform.dmp 25KB
compile.do 747B
compile.do 723B
compile.do 682B
compile.do 672B
simulate.do 303B
simulate.do 294B
simulate.do 294B
simulate.do 187B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 456B
run.f 440B
usage_statistics_webtalk.html 150KB
hw_ila_data_1.ila 328KB
xsim.ini 22KB
vivado_5032.backup.jou 39KB
vivado_2956.backup.jou 27KB
vivado_14780.backup.jou 9KB
vivado_4092.backup.jou 4KB
vivado.jou 1015B
vivado.jou 706B
vivado_6996.backup.jou 706B
vivado.jou 702B
vivado.jou 700B
vivado_11456.backup.jou 697B
循环读AD时序图.jpg 117KB
drdy信号.jpg 81KB
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
hw_ila_1.layout 205KB
replay_pid21044.log 745KB
vivado_5032.backup.log 279KB
runme.log 156KB
vivado_2956.backup.log 126KB
hs_err_pid21044.log 104KB
vivado_4092.backup.log 103KB
hs_err_pid8260.log 69KB
runme.log 54KB
runme.log 47KB
vivado_14780.backup.log 45KB
vivado.log 20KB
vivado_11456.backup.log 1KB
TM7705.lpr 343B
debug_nets.ltx 13KB
TM7705_top.ltx 13KB
probes.ltx 7KB
elab.opt 180B
vivado.pb 250KB
vivado.pb 78KB
vivado.pb 37KB
opt_design.pb 18KB
place_design.pb 17KB
route_design.pb 14KB
init_design.pb 14KB
write_bitstream.pb 13KB
messagePromote.pb 2KB
TM7705_top_power_summary_routed.pb 722B
ila_0_utilization_synth.pb 224B
TM7705_top_utilization_synth.pb 224B
TM7705_top_utilization_placed.pb 224B
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