Zynq-7000 PCB Design Guide www.xilinx.com 3
UG933 (v1.13.1) March 14, 2019
12/04/2013 1.6
Changed “DDR3” to “DDR3/3L” throughout document. Updated capacitor quantities
and packages in Tab l e 3-1 and Ta ble 3-2. Updated capacitor specifications in
Table 3-3 . Updated descriptions for V
CCPINT
– PS Internal Logic Supply and V
CCPAUX
–
PS Auxiliary Logic Supply. Deleted “Capacitor Consolidation Rules” section. Modified
next-to-last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference
Voltage. Added paragraph preceding Ta b le 5-5 and updated Ta b l e 5-5. Updated Addr,
Command, Contrl output name in Figure 5-7. Deleted last sentence under DDR Trace
Length.
08/01/2014 1.7
Removed “and Pin Planning Guide” from title. Added recommendation to
Recommended PCB Capacitors per Device. Changed V
CCO
per Bank sub-heading from
“100 µF” to 47 µF” in Tabl e 3-1. Removed values for V
CCPLL
and replaced with
reference (Note 3) in Ta ble 3-2. Changed “Terminal” type to “Terminal Tantalum” and
added “X7U” to 100 µF capacitor in Table 3-3. Modified first paragraph under Noise
Limits by removing specifications and adding a reference to the data sheet. Updated
second paragraph under Unconnected V
CCO
Pins. Changed Murata part number from
“GRM155R60J475ME47D” to “GRM155R60J474KE19” under Unconnected V
CCO
Pins.
Updated first paragraph under PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination
Voltage. Updated Unused DDR Memory. Deleted last two sentences under PS_POR_B
– Power on Reset and last sentence under PS_SRST_B – External System Reset.
Changed “Boot Mode Pins” section (pins MIO[2] to MIO[8] to Boot Mode Pins.
Modified Figure 5-5 (CKE resistor layout). Modified Figure 5-6 (changed clk signal to
differential signals CLK_P/CLK_N and added pull-down resistor to ODT). Added
separate column for DDR3L to Ta b le 5-6 and modified values. Clarified DDR Trace
Length and DDR Trace Impedance sections. Clarified byte swapping under DDR
Routing Topology. Added last paragraph under Ethernet GEM. Deleted “Lower
Operating Frequencies (without Feedback Mode)” section from Chapter 6.
08/05/2014 1.7.1
Updated document to latest user guide template.
11/07/2014 1.8
Added XC7Z035 device to Ta b l e 3-1 and Tabl e 3-2. Added 10 µF capacitor to Table 3-3 .
Updated Table 5-5.
05/22/2015 1.9
Added Note under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference Voltage.
Added Caution following Table 5-3. Clarified Boot Mode Pins (changed first instance
of MIO[8] to MIO[8:2]. Updated Tabl e 5-8. Clarified paragraph following Table 5-9.
Deleted last sentence under IIC. Clarified first paragraph under SDIO and second
sentence under UART. Deleted the word “maximum” preceding “hold time” in the
Important notice under QSPI.
09/25/2015 1.10
Added packages SBV485, FBV484, FBV676, and FFV676 to device XC7Z030, packages
FBV676, FFV676 and FFV900 to device XC7Z035, packages FBV676, FFV676, RFG676,
and FFV900 to device Z-7045, and packages FFV900, RF900, FFV1156, and RF1156 to
device XC7Z100 in Ta b le 3-2. Added Bulk Capacitor Consolidation Rules in Chapter 3.
Deleted caution preceding Table 5-3. Updated requirements for PS_POR_B – Power on
Reset in Chapter 5. Updated DDR Routing Topology in Chapter 5. Added package
SBV485 to device Z-7100 in Differences between XC7Z030-SBG485/SBV485,
XC7Z015-CLG485, and XC7Z012S-CLG485 Devices in Chapter 6. Added Appendix A,
Processing System Memory Derating Tables.
03/31/2016 1.11
Added recommendations to IIC and SDIO in Chapter 5.
09/27/2016 1.12
Added single core devices XC7Z007S, XC7Z012S, and XC7Z014S to Table 3-1,
Table 3-2 , and throughout text. Added migration information from XC7Z030-SBG485
to XC7012S-CLG485 devices in Chapter 6, updated Tab le 6- 1 , and added Processor
Differences in Chapter 6.
Date Version Revision
