gSim51 - 8051 microcontroller simulator-开源

//#ifndef _PASS1_ //#define _PASS1_ //#endif #include"gas51.h" /* gas51_symbol_table[100] = { {"A",0xe0}, {"B",0xf0} }; */ struct instruct { int hex_code; const char *mnemonic; int nobytes; // int clock; //int noperands; // void (*ins_ptr)(int); }; //struct instruct instructions; struct instruct instructions[]={ {0X0,"NOP",1}, // {0X1,"AJMP ADDR",2}, {0X2,"LJMP ADDR",3}, // {0X3,"RR A",1}, // {0X4,"INC A",1},// /*'X' denotes dummy args. for simulator*/ {0X5,"INC ADDR",2},// /*A means address,*/ {0X6,"INC @R0",1},// /*D means data*/ {0X7,"INC @R1",1},// /*C means code*/ {0X8,"INC R0",1}, // {0X9,"INC R1",1}, // {0XA,"INC R2",1},// {0XB,"INC R3",1}, // {0XC,"INC R4",1}, // {0XD,"INC R5",1}, // {0XE,"INC R6",1},// {0XF,"INC R7",1}, // {0X10,"JBC ADDR,ADDR",3}, {0X11,"ACALL ADDR",2}, {0X12,"LCALL ADDR",3}, {0X13,"RRC A",1}, // {0X14,"DEC A",1}, // {0X15,"DEC ADDR",2}, // {0X16,"DEC @R0",1}, // {0X17,"DEC @R1",1}, // {0X18,"DEC R0",1}, // {0X19,"DEC R1",1}, // {0X1A,"DEC R2",1}, // {0X1B,"DEC R3",1}, // {0X1C,"DEC R4",1}, // {0X1D,"DEC R5",1}, // {0X1E,"DEC R6",1}, // {0X1F,"DEC R7",1}, // {0X20,"JB ADDR,ADDR",3}, {0X21,"AJMP ADDR",2}, {0X22,"RET",1}, {0X23,"RL A",1}, // {0X24,"ADD A,#DATA",2}, // {0X25,"ADD A,ADDR",2}, // {0X26,"ADD A,@R0 ",1}, // {0X27,"ADD A,@R1 ",1}, // {0X28,"ADD A,R0",1}, // {0X29,"ADD A,R1",1},// {0X2A,"ADD A,R2",1}, // {0X2B,"ADD A,R3",1},// {0X2C,"ADD A,R4",1}, // {0X2D,"ADD A,R5",1}, // {0X2E,"ADD A,R6",1}, // {0X2F,"ADD A,R7",1}, // {0X30,"JNB ADDR,ADDR",3}, {0X31,"ACALL ADDR",2}, {0X32,"RETI",1}, {0X33,"RLC A",1}, {0X34,"ADDC A,#DATA",2}, {0X35,"ADDC A,ADDR",2}, {0X36,"ADDC A,@R0 ",1}, {0X37,"ADDC A,@R1 ",1}, {0X38,"ADDC A,R0",1}, {0X39,"ADDC A,R1",1}, {0X3A,"ADDC A,R2",1}, {0X3B,"ADDC A,R3",1}, {0X3C,"ADDC A,R4",1}, {0X3D,"ADDC A,R5",1}, {0X3E,"ADDC A,R6",1}, {0X3F,"ADDC A,R7",1}, {0X40,"JC ADDR,ADDR",2}, {0X41,"AJMP ADDR",2}, {0X42,"ORL ADDR,A",2}, {0X43,"ORL ADDR,#DATA",3}, {0X44,"ORL A,#DATA",2}, {0X45,"ORL A,ADDR",2}, {0X46,"ORL A,@R0 ",1}, {0X47,"ORL A,@R1 ",1}, {0X48,"ORL A,R0",1}, {0X49,"ORL A,R1",1}, {0X4A,"ORL A,R2",1}, {0X4B,"ORL A,R3",1}, {0X4C,"ORL A,R4",1}, {0X4D,"ORL A,R5",1}, {0X4E,"ORL A,R6",1}, {0X4F,"ORL A,R7",1}, {0X50,"JNC ADDR,ADDR",2}, {0X51,"ACALL ADDR",2}, {0X52,"ANL ADDR,A",2}, {0X53,"ANL ADDR,#DATA",3}, {0X54,"ANL A,#DATA",2}, {0X55,"ANL A,ADDR",2}, {0X56,"ANL A,@R0 ",1}, {0X57,"ANL A,@R1 ",1}, {0X58,"ANL A,R0",1}, {0X59,"ANL A,R1",1}, {0X5A,"ANL A,R2",1}, {0X5B,"ANL A,R3",1}, {0X5C,"ANL A,R4",1}, {0X5D,"ANL A,R5",1}, {0X5E,"ANL A,R6",1}, {0X5F,"ANL A,R7",1}, {0X60,"JZ ADDR",2}, {0X61,"AJMP ADDR",2}, {0X62,"XRL ADDR,A",2}, {0X63,"XRL ADDR,#DATA",3}, {0X64,"XRL A,#DATA",2}, {0X65,"XRL A,ADDR",2}, {0X66,"XRL A,@R0",1}, {0X67,"XRL A,@R1",1}, {0X68,"XRL A,R0",1}, {0X69,"XRL A,R1",1}, {0X6A,"XRL A,R2",1}, {0X6B,"XRL A,R3",1}, {0X6C,"XRL A,R4",1}, {0X6D,"XRL A,R5",1}, {0X6E,"XRL A,R6",1}, {0X6F,"XRL A,R7",1}, {0X70,"JNZ ADDR",2}, {0X71,"ACALL ADDR",2}, {0X72,"ORL C,ADDR",2}, {0X73,"JMP @A+DPTR",1}, {0X74,"MOV A,#DATA",2}, /*MOV DATAADDR,#DATA*/ {0X75,"MOV ADDR,#DATA",3}, {0X76,"MOV @R0,#DATA",2}, {0X77,"MOV @R1,#DATA",2}, {0X78,"MOV R0,#DATA",2}, {0X79,"MOV R1,#DATA",2}, {0X7A,"MOV R2,#DATA",2}, {0X7B,"MOV R3,#DATA",2}, {0X7C,"MOV R4,#DATA",2}, {0X7D,"MOV R5,#DATA",2}, {0X7E,"MOV R6,#DATA",2}, {0X7F,"MOV R7,#DATA",2}, {0X80,"SJMP ADDR",2}, {0X81,"AJMP ADDR",2}, {0X82,"ANL C,ADDR",2}, {0X83,"MOVC A,@A+PC ",1}, {0X84,"DIV AB",1}, {0X85,"MOV ADDR,ADDR",3}, {0X86,"MOV ADDR,@R0",2}, {0X87,"MOV ADDR,@R1",2}, {0X88,"MOV ADDR,R0",2}, {0X89,"MOV ADDR,R1",2}, {0X8A,"MOV ADDR,R2",2}, {0X8B,"MOV ADDR,R3",2}, {0X8C,"MOV ADDR,R4",2}, {0X8D,"MOV ADDR,R5",2}, {0X8E,"MOV ADDR,R6",2}, {0X8F,"MOV ADDR,R7",2}, {0X90,"MOV DPTR,#DATA",3}, {0X91,"ACALL ADDR",2}, {0X92,"MOV ADDR,C",2}, {0X93,"MOVC A,@A+DPTR",1}, {0X94,"SUBB A,#DATA",2}, {0X95,"SUBB A,ADDR",2}, {0X96,"SUBB A,@R0 ",1}, {0X97,"SUBB A,@R1 ",1}, {0X98,"SUBB A,R0",1}, {0X99,"SUBB A,R1",1}, {0X9A,"SUBB A,R2",1}, {0X9B,"SUBB A,R3",1}, {0X9C,"SUBB A,R4",1}, {0X9D,"SUBB A,R5",1}, {0X9E,"SUBB A,R6",1}, {0X9F,"SUBB A,R7",1}, {0XA0,"ORL C,/ADDR",2}, {0XA1,"AJMP ADDR",2}, {0XA2,"MOV C,ADDR",2}, {0XA3,"INC DPTR",1}, {0XA4,"MUL AB",1}, {0XA5," ",0}, // no instruction for this opcode...nobytes changed to 0..necessary... {0XA6,"MOV @R0,ADDR",2}, {0XA7,"MOV @R1,ADDR",2}, {0XA8,"MOV R0,ADDR",2}, {0XA9,"MOV R1,ADDR",2}, {0XAA,"MOV R2,ADDR",2}, {0XAB,"MOV R3,ADDR",2}, {0XAC,"MOV R4,ADDR",2}, {0XAD,"MOV R5,ADDR",2}, {0XAE,"MOV R6,ADDR",2}, {0XAF,"MOV R7,ADDR",2}, {0XB0,"ANL C,/ADDR",2}, {0XB1,"ACALL ADDR",2}, {0XB2,"CPL ADDR",2}, {0XB3,"CPL C",1}, {0XB4,"CJNE A,#DATA,ADDR",3}, {0XB5,"CJNE A,ADDR,ADDR",3}, {0XB6,"CJNE @R0,#DATA,ADDR",3}, {0XB7,"CJNE @R1,#DATA,ADDR",3}, {0XB8,"CJNE R0,#DATA,ADDR",3}, {0XB9,"CJNE R1,#DATA,ADDR",3}, {0XBA,"CJNE R2,#DATA,ADDR",3}, {0XBB,"CJNE R3,#DATA,ADDR",3}, {0XBC,"CJNE R4,#DATA,ADDR",3}, {0XBD,"CJNE R5,#DATA,ADDR",3}, {0XBE,"CJNE R6,#DATA,ADDR",3}, {0XBF,"CJNE R7,#DATA,ADDR",3}, {0XC0,"PUSH ADDR",2}, {0XC1,"AJMP ADDR",2}, {0XC2,"CLR ADDR",2,}, {0XC3,"CLR C",1}, {0XC4,"SWAP A",1}, {0XC5,"XCH A,ADDR",2}, {0XC6,"XCH A,@R0",1}, {0XC7,"XCH A,@R1",1}, {0XC8,"XCH A,R0",1}, {0XC9,"XCH A,R1",1}, {0XCA,"XCH A,R2",1}, {0XCB,"XCH A,R3",1}, {0XCC,"XCH A,R4",1}, {0XCD,"XCH A,R5",1}, {0XCE,"XCH A,R6",1}, {0XCF,"XCH A,R7",1}, {0XD0,"POP ADDR",2}, {0XD1,"ACALL ADDR",2}, {0XD2,"SETB ADDR",2}, {0XD3,"SETB C",1}, {0XD4,"DA A",1}, {0XD5,"DJNZ ADDR,ADDR",3}, {0XD6,"XCHD A,@R0",1}, {0XD7,"XCHD A,@R1",1}, {0XD8,"DJNZ R0,ADDR",2}, {0XD9,"DJNZ R1,ADDR",2}, {0XDA,"DJNZ R2,ADDR",2}, {0XDB,"DJNZ R3,ADDR",2}, {0XDC,"DJNZ R4,ADDR",2}, {0XDD,"DJNZ R5,ADDR",2}, {0XDE,"DJNZ R6,ADDR",2}, {0XDF,"DJNZ R7,ADDR",2}, {0XE0,"MOVX A,@DPTR",1}, {0XE1,"AJMP ADDR",2}, {0XE2,"MOVX A,@R0",1}, {0XE3,"MOVX A,@R1",1}, {0XE4,"CLR A",1}, {0XE5,"MOV A,ADDR",2}, {0XE6,"MOV A,@R0",1}, {0XE7,"MOV A,@R1",1}, {0XE8,"MOV A,R0",1}, {0XE9,"MOV A,R1",1}, {0XEA,"MOV A,R2",1}, {0XEB,"MOV A,R3",1}, {0XEC,"MOV A,R4",1}, {0XED,"MOV A,R5",1}, {0XEE,"MOV A,R6",1}, {