开源指令集架构RISCV文档和常用指令介绍和总结

RISCV

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RISC-V Instruction Set Summary

CONTENT

.............................................................................................................................................

Revision History

..............................................................................................................................

1 Register File

......................................................................................................................................

1.1 GPR

........................................................................................................................................

1.2 FGPR

......................................................................................................................................

1.3 Vector Registers

.....................................................................................................................

1.3.1 Vector CSRs

.................................................................................................................

1.3.1.1 Vector type register (vtype)

............................................................................

1.3.1.2 Vector Length Register (vl)

..............................................................................

1.3.2 Vector General Purpose Registers (VGPR)

.................................................................

1.3.3 Mapping of Vector Elements to Vector Register State

..............................................

1.3.3.1 Mapping with LMUL=1

....................................................................................

1.3.3.2 Mapping with LMUL > 1

..................................................................................

1.3.3.3 Mask Register Layout

......................................................................................

1.4 PC

...........................................................................................................................................

1.5 CSRs

.......................................................................................................................................

2 RISCV32-IMACF Instructions

..........................................................................................................

2.1 RISCV32-I

.............................................................................................................................

2.1.1 Load and Store Instructions

.....................................................................................

2.1.1.1 lb rd, offset(rs1)

............................................................................................

2.1.1.2 lbu rd, offset(rs1)

..........................................................................................

2.1.1.3 lh rd, offset(rs1)

............................................................................................

2.1.1.4 lhu rd, offset(rs1)

..........................................................................................

2.1.1.5 lw rd, offset(rs1)

............................................................................................

2.1.1.6 sb rs2, offset(rs1)

...........................................................................................

2.1.1.7 shrs2, offset(rs1)

...........................................................................................

2.1.1.8 swrs2, offset(rs1)

..........................................................................................

2.1.2 Integer Computational Instructions

.........................................................................

2.1.2.1 sllrd, rs1, rs2

..................................................................................................

2.1.2.2 slli rd, rs1, shamt

...........................................................................................

2.1.2.3 srl rd, rs1, rs2

.................................................................................................

2.1.2.4 srlird, rs1, shamt

...........................................................................................

2.1.2.5 sra rd, rs1, rs2

................................................................................................

2.1.2.6 sraird, rs1, shamt

..........................................................................................

2.1.2.7 addrd, rs1, rs2

...............................................................................................

2.1.2.8 addi rd, rs1, immediate

................................................................................

2.1.2.9 sub rd,rs1, rs2

................................................................................................

2.1.2.10 lui rd, immediate

.........................................................................................

2.1.2.11 auipc rd, immediate

....................................................................................

2.1.2.12 and rd, rs1, rs2

.............................................................................................

2.1.2.13 andi rd, rs1, immediate

..............................................................................

2.1.2.14 or rd, rs1, rs2

................................................................................................

2.1.2.15 orird, rs1, immediate

..................................................................................

2.1.2.16 xor rd, rs1, rs2

..............................................................................................

2.1.2.17 xorird, rs1, immediate

................................................................................

2.1.2.18 sltrd, rs1, rs2

................................................................................................

2.1.2.19 slturd, rs1, rs2

..............................................................................................

2.1.2.20 slti rd, rs1, immediate

.................................................................................

2.1.2.21 sltiu rd, rs1, immediate

...............................................................................

2.1.3 Control Transfer Instructions

...................................................................................

2.1.3.1 beq rs1, rs2, offset

........................................................................................

2.1.3.2 bne rs1, rs2, offset

........................................................................................

2.1.3.3

blt

rs1, rs2, offset

...........................................................................................

2.1.3.4

bge

rs1, rs2, offset

........................................................................................

2.1.3.5

bltu

rs1, rs2, offset

........................................................................................

2.1.3.6 bgeu rs1, rs2, offset

......................................................................................

2.1.3.7 jal rd, offset

....................................................................................................

2.1.3.8 jalr rd, offset(rs1)

..........................................................................................

2.1.4 Misc-mem instructions

............................................................................................

2.1.4.1

fence

pred, succ

.............................................................................................

2.1.4.2 fence.i

............................................................................................................

2.1.4.3 sfence.vmars1, rs2

.........................................................................................

2.1.5 Control and Status Register Instructions

.................................................................

2.1.5.1 csrrw rd, csr, zimm[4:0]

................................................................................

2.1.5.2 csrrs rd, csr, rs1

..............................................................................................

2.1.5.3 csrrc rd, csr, rs1

..............................................................................................

2.1.5.4 csrrwi rd, csr, zimm[4:0]

...............................................................................

2.1.5.5 csrrsi rd, csr, zimm[4:0]

.................................................................................

2.1.5.6 csrrci rd, csr, zimm[4:0]

.................................................................................

2.1.6 Environment Call and Breakpoints

..........................................................................

2.1.6.1 ecall

...............................................................................................................

2.1.6.2 ebreak

...........................................................................................................

2.1.7 Trap-Return Instructions

..........................................................................................

2.1.7.1 mret

...............................................................................................................

2.1.7.2 sret

................................................................................................................

2.1.8 Wait for Interrupt

.....................................................................................................

2.1.8.1 wfi

..................................................................................................................

2.2 RISCV32-M

...........................................................................................................................

2.2.1 mul rd, rs1, rs2

..........................................................................................................

2.2.2 mulh rd, rs1, rs2

........................................................................................................

2.2.3 mulhsu rd,rs1, rs2

.....................................................................................................

2.2.4 mulhu rd, rs1, rs2

......................................................................................................

2.2.5

div

rd, rs1, rs2

...........................................................................................................

2.2.6

divu

rd, rs1, rs2

.........................................................................................................

2.2.7 rem rd, rs1, rs2

.........................................................................................................

2.2.8 remu rd, rs1, rs2

.......................................................................................................

2.3 RISCV32-C

............................................................................................................................

2.3.1 Load and Store Instructions

.....................................................................................

2.3.1.1 c.lwrd’, uimm(rs1’)

........................................................................................

2.3.1.2 c.swrs2’, uimm(rs1’)

......................................................................................

2.3.1.3 c.lwsp rd, uimm(x2)

.....................................................................................

2.3.1.4 c.swsprs2, uimm(x2)

.....................................................................................

2.3.2 Control Transfer Instructions

...................................................................................

2.3.2.1 c.beqzrs1’, offset

...........................................................................................

2.3.2.2 c.bnezrs1’, offset

...........................................................................................

2.3.2.3 c.j offset

.........................................................................................................

2.3.2.4 c.jr rs1

............................................................................................................

2.3.2.5 c.jal offset

......................................................................................................

2.3.2.6 c.jalr rs1

.........................................................................................................

2.3.2.7 c.ebreak

.........................................................................................................

2.3.3 Integer Computational Instructions

.........................................................................

2.3.3.1 c.add rd, rs2

...................................................................................................

2.3.3.2 c.addird, imm

................................................................................................

2.3.3.3 c.subrd’, rs2’

..................................................................................................

2.3.3.4 c.addi16spimm

.............................................................................................

2.3.3.5 c.addi4spn rd’, uimm

.....................................................................................

2.3.3.6 c.and rd’, rs2’

.................................................................................................

2.3.3.7 c.andird’, imm

...............................................................................................

2.3.3.8 c.orrd’, rs2’

....................................................................................................

2.3.3.9 c.xorrd’, rs2’

...................................................................................................

2.3.3.10 c.sllird, uimm

...............................................................................................

2.3.3.11 c.srlird’, uimm

..............................................................................................

2.3.3.12 c.sraird’, uimm

.............................................................................................

2.3.3.13 c.mvrd, rs2

.................................................................................................

2.3.3.14 c.lird, imm

...................................................................................................

2.3.3.15 c.luird, imm

.................................................................................................

2.3.4 Floating Point Instructructions

.................................................................................

2.3.4.1 c.flwrd’, uimm(rs1’)

.......................................................................................

2.3.4.2 c.flwsprd, uimm(x2)

......................................................................................

2.3.4.3 c.fsw rs2’, uimm(rs1’)

....................................................................................

2.3.4.4 c.fswsp rs2, uimm(x2)

...................................................................................

2.4 RISCV-F

................................................................................................................................

2.4.1 Single-Precision Floating-Point Load and Store Instructions

...................................

2.4.1.1 flw rd, offset(rs1)

..........................................................................................

2.4.1.2 fsw rs2, offset(rs1)

..........................................................................................

2.4.2 Single-Precision Floating-Point Computational Instructions

...................................

2.4.2.1 fmadd.s rd, rs1, rs2, rs3

.................................................................................

2.4.2.2 fmsub.s rd, rs1, rs2, rs3

..................................................................................

2.4.2.3 fnmadd.s rd, rs1, rs2, rs3

...............................................................................

2.4.2.4 fnmsub.srd, rs1, rs2, rs3

................................................................................

2.4.2.5 fadd.s rd, rs1, rs2

...........................................................................................

2.4.2.6 fsub.s rd,rs1, rs2

............................................................................................

2.4.2.7 fmul.s rd, rs1, rs2

...........................................................................................

2.4.2.8 fdiv.s rd, rs1, rs2

.............................................................................................

2.4.2.9

fsqrt

.s rd, rs1, rs2

...........................................................................................

2.4.2.10 fmin.s rd,rs1, rs2

..........................................................................................

2.4.2.11 fmax.s rd,rs1, rs2

.........................................................................................

2.4.3 Single-Precision Floating-Point Conversion and Move Instructions

........................

2.4.3.1

fcvt

.w.s rd, rs1, rs2

.........................................................................................

2.4.3.2 fcvt.wu.s rd, rs1, rs2

.......................................................................................

2.4.3.3

fcvt

.s.w rd, rs1, rs2

.........................................................................................

2.4.3.4

fcvt

.s.wu rd, rs1, rs2

.......................................................................................

2.4.3.5 fsgnj.s rd, rs1, rs2

...........................................................................................

2.4.3.6 fsgnjn.s rd, rs1, rs2

.........................................................................................

2.4.3.7 fsgnjx.s rd, rs1, rs2

.........................................................................................

2.4.3.8 fmv.x.w rd, rs1, rs2

.........................................................................................

2.4.3.9 fmv.w.x rd, rs1, rs2

.........................................................................................

2.4.4 Single-Precision Floating-Point Compare Instructions

............................................

2.4.4.1 feq.s rd, rs1, rs2

..............................................................................................

2.4.4.2 flt.s rd, rs1, rs2

...............................................................................................

2.4.4.3 fle.s rd, rs1, rs2

...............................................................................................

2.4.5 Single-Precision Floating-Point Classify Instruction

.................................................

2.4.5.1

fclass

.s rd, rs1

................................................................................................

3 RISCV64-IMACD Instructions

..........................................................................................................

3.1 RISCV64-I

.............................................................................................................................

3.1.1 lwu rd, offset(rs1)

.....................................................................................................

3.1.2 ld rd, offset(rs1)

........................................................................................................

3.1.3 sd rs2, offset(rs1)

.....................................................................................................

3.1.4 addw rd, rs1, rs2

.......................................................................................................

3.1.5 addiw rd, rs1, immediate

.........................................................................................

3.1.6 subw rd, rs1, rs2

.......................................................................................................

3.1.7 sllw rd, rs1, rs2

..........................................................................................................

3.1.8 slliw rd, rs1, shamt

...................................................................................................

3.1.9 sraw rd,rs1, rs2

.........................................................................................................

3.1.10 sraiw rd,rs1, shamt

................................................................................................

3.1.11 srliw rd, rs1, shamt

.................................................................................................

3.1.12 srlw rd, rs1, rs2

.......................................................................................................

3.2 RISCV64-M

...........................................................................................................................

3.2.1 mulw rd, rs1, rs2

.......................................................................................................

3.2.2

divw

rd, rs1, rs2

........................................................................................................

3.2.3

divuw

rd, rs1, rs2

......................................................................................................

3.2.4 remw rd, rs1, rs2

.......................................................................................................

3.2.5 remuw rd, rs1, rs2

....................................................................................................

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