UG476 (v1.12) December 19, 2016 www.xilinx.com 7 Series FPGAs GTX/GTH Transceivers User Guide
04/04/2012 1.4
(Cont’d)
Chapter 4: Updated Table 4-2. Updated GTX and GTH Use Modes—RX Termination
and RX Equalizer (DFE and LPM). In Table 4-11 and Table 4-15, replaced
RXDFEOSHOLD, RXDFEOSOVRDEN, and RX_DFE_OS_CFG with RXOSHOLD,
RXOSOVRDEN, and RX_OS_CFG, respectively. In Table 4-11, merged RX_DFE_LPM
and HOLD_DURING_EIDLE into RX_DFE_LPM_HOLD_DURING_EIDLE, and
removed IAS_CFG. Added GTX Use Modes, including Figure 4-20, Table 4-12, and
Table 4-13. Updated Figure 4-23, including note 2. In Table 4-26, added RXLPMEN. In
Table 4-27, removed A_RXLPMEN, updated ES_EYE_SCAN_EN, and added
PMA_RSV2[5], USE_PCS_CLK_PHASE_SEL, and ES_CLK_PHASE_SEL. Updated
description of RX_PRBS_ERR_CNT in Table 4-31. Updated Alignment Status Signals
and Manual Alignment. Updated description of RXBYTEISALIGNED in Table 4-32.
Added COMMA_ALIGN_LATENCY to Table 4-33. Added sentence about use of
RXSLIDE_MODE to RX Buffer Bypass. In Table 4-36, updated description of
RXPHDLYPD, and added RXSYNCMODE, RXSYNCALLIN, RXSYNCIN,
RXSYNCOUT, and RXSYNCDONE. In Table 4-37, added RXSYNC_MULTI_LANE,
RXSYNC_SKIP_DA, and RXSYNC_OVRD. Updated Using RX Buffer Bypass in
Single-Lane Auto Mode (GTX Transceiver Only) heading. Updated notes after
Figure 4-45. Updated description of FTS_LANE_DESKEW_CFG in Table 4-48. Updated
Functional Description, page 283. In Table 4-49, updated descriptions of
RXDATAVALID, RXGEARBOXSLIP, RXHEADER, RXHEADERVALID, and
RXSTARTOFSEQ, and added RXSLIDE. Updated description of GEARBOX_MODE in
Table 4-50. Added normal mode to RX Gearbox Operating Modes. Updated Figure 4-65
and RX Gearbox Block (GTH Transceiver).
Chapter 5: Updated Table 5-1, Table 5-6, and Table 5-7. Added LVDS, including
Figure 5-8. In Figure 5-9
, updated value of capacitors from 0.01 μF to 0.1 μF.
Chapter 6: Updated Functional Description, including Table 6-1. Updated description of
RXELECIDLE in Table 6-2. Updated [TX/RX]RATE[2:0] setting in Table 6-4. Updated
[TX/RX]OUT_DIV setting in Table 6-6. Updated QPLL_FBDIV setting in Table 6-7.
PCLK frequency in Parallel Clock (PCLK). Updated Rate Change to Enter or Exit Gen3
Speed. Updated PCI Express Clock Correction. In Table 6-12, updated value of
[TX/RX]_CLK25_DIV from 2 to 7.
Appendix A: Added sentence about leaded package options to first paragraph. Added
GTH Transceiver Package Placement Diagrams.
Appendix B: Added Table B-3.
Appendix D: Updated Table D-1 and Table D-2. Added Table D-3 and Table D-4.
05/07/2012 1.5 Chapter 5: Updated recommendations for MGTVCCAUX_G[N] in Table 5-7.
Appendix A: Corrected labels in Figure A-50, Figure A-61, Figure A-63, Figure A-91,
and Figure A-92.
09/11/2012 1.6 Chapter 2: Updated Figure 2-1. Updated CLKSWING_CFG in Table 2-2. Added
GTREFCLKMONITOR to Table 2-4. Added OUTREFCLK_SEL_INV to Table 2-5.
Added REFCLKOUTMONITOR to Table 2-6. Added Single External Reference Clocks
Use Model and Multiple External Reference Clocks Use Model. Updated Channel PLL
and Quad PLL. Added note to Table 2-10. Added QPLL Settings for Common Protocols.
Updated Table 2-12
. Removed QPLL_CFG from Attribute column for Factor N in
Table 2-13. Added Table 2-27 and descriptions of reset situations. Updated description
of RXRESETDONE in Table 2-28. Replaced RXCDRRESET_TIME with
RXCDRPHRESET_TIME in Table 2-29. Added Table 2-32 and descriptions of reset
situations. Updated description of loopback modes in Loopback. Updated description
of DMONITOR_CFG[23:0] and added RX_DEBUG_CFG, PCS_RSVD_ATTR[6], and
CFOK_CFG[41] to Table 2-41. Updated Verilog code in Capturing the Digital Monitor
Output. In Interpreting the Digital Monitor Output, added bullet for RXDFELF[3:0] and
updated
RXDFEAGC[3:0] for GTX and GTH transceivers.
Date Version Revision
