################################################################################
# Vivado (TM) v2020.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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『FPGA通信接口』串行通信接口-SPI (590个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
spi_top.bit 2.09MB
spi_top_routed.dcp 2.94MB
spi_top_physopt.dcp 2.58MB
spi_top_placed.dcp 2.57MB
spi_top_opt.dcp 2.03MB
ila_0.dcp 669KB
ila_0.dcp 668KB
ila_0.dcp 668KB
ila_0.dcp 615KB
ila_1.dcp 583KB
ila_1.dcp 583KB
ila_1.dcp 582KB
dbg_hub.dcp 356KB
dbg_hub.dcp 346KB
spi_top.dcp 46KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
compile.do 814B
compile.do 814B
compile.do 800B
compile.do 790B
compile.do 790B
compile.do 776B
compile.do 758B
compile.do 758B
compile.do 748B
compile.do 748B
compile.do 744B
compile.do 734B
simulate.do 304B
simulate.do 299B
simulate.do 299B
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simulate.do 296B
simulate.do 287B
simulate.do 287B
simulate.do 287B
simulate.do 287B
simulate.do 188B
elaborate.do 183B
simulate.do 180B
simulate.do 180B
elaborate.do 175B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
run.f 598B
run.f 582B
run.f 504B
run.f 504B
run.f 488B
run.f 488B
usage_statistics_webtalk.html 274KB
hw_ila_data_1.ila 33KB
hw_ila_data_2.ila 24KB
xsim.ini 29KB
xsim.ini 29KB
xsim.ini 29KB
vivado_15340.backup.jou 15KB
vivado.jou 912B
vivado_21868.backup.jou 907B
vivado_14244.backup.jou 907B
vivado.jou 884B
vivado.jou 855B
vivado.jou 850B
vivado.jou 846B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
hw_ila_1.layout 171KB
runme.log 45KB
runme.log 27KB
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