Cyclone V 官方开发板原理图

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Cyclone V 官方开发板原理图,Cadence,适合FPGA开发者参考
PCI Express Connector 3.3v 12 EXP 3.3vE 12V EXP 3.3V EXP PRSNT1 N +12V T9)PCIE SMBDAT SMCLK ITAG TCK R7入4K二 GND JTAG TMS FCIE WAKEn(11 4.11)PcE WAK三N PERST N B12 0)PcER三 FCLK SYN P 10)PMER三 CLK SYN卜 A16 8)PCI RX F0 PCIE PRSNT2×1(9 PRSNT2 N X1 PERON HA17-(8)PCIE RX NO GND 证 B21 PETIN x4 RSVD2 7419 PE T1P END PERIN A22 (8)PCIE RX N1 「匙d等 PCIE TX C P2 ET∠N 26 ( 8)PCI RX F2 6(8Pe FCIE TX P3(8 C638 ID.1LF PCIE_TX C_P3 FG正XN3(6 〔6D1∥ F PCIE_TX_C_N PET3P FFR3P 8)PCIE RX N PCIE PRSNT2×4(9 PRSNT2 N K4 GN PCIE 06202F-D TH 12V EXP 3.3V EXP C232 211F= 220uF 2201F 47UF 25V 16V Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 e Cyclone V SoC FPGA Development Kit Board NALERA Altera Corporation. All Rights Reserved 150-0321003D16X×-44184R)P1 Pate: Thursday November 21, 2013 heet Cyclone v GX Soc Bank 3 &4 5,19)EN 419,21)ENET_ DUAL RESE CYCLONE V GX SOC BANK 4 100.1% DDR3 FPGA DQ2 AG 6 Bank 4A R449 CYCLONE V GX SOC bANK 3 DIFFIO TX B41p, DC6E, B Q 2 RZQ O.DIFFIO Tx B4In DDR AE7 DIFFIO B42p, DQGB, B CQ 1 DIFFI R3FPeAB2 HSMA DO DIFF IO RX BO2n, DQBBE DQ 20 DIFF B43n. DQSn6B, B DQS: 0 FEIO AG DIFFIO TX B9p, D02B DIFFIO TX B64p, DQ8B, B DM 2 DDR3 FPGA DI FFIO RX B10p, DQ2B DIFFIO RX B14P, DQ2B DIFFIO Rx B14n, DQ2B 12DIFFIO-RX B100, D02B DIFFIO TX R45n. DE6BB ODT FFlO TX B65n GND DIFF IO RX B66p, DQ9BE DQ 8111. DQS112B DIF-IO TX B18p, DQ AC3820 DIFFIO TX B16IL. DQ2B DIFFIO RX B6 DIFFIC QSn9B. B L Q 1C DIFFIO TX BBD.DOB E DO 27 USER DIPSW FPGAO 0 30 AG75 DDRS FPGA DO30 OIFFIO_TX B17p, DQ3B B:an:k 3B AB15 CDR3 FPGA CSnl A石X知,BCQ9 DIFFIO TX B69P, DQ9B, E DO DIFFN TX B17n DIFO RX 77 OSh4R B CSe o FAc DIFFIO RX B50n, DO7B B DO 8 DIFFIO TX B69n, Da9B, G E22 DDR3 FPGA DQ29 DIFFIO RX OIFFIO RX B18p, DQ3B DIF FIO RX B5n. DQSn7B, B DOS# 1 DIFFIO R B7ONDQ9BE DQ 28 USER DIFFIO TX E28r1,D DDR3 FPGA DQ11 DIFFIO RX B FFIO RX B19n. DQSn 3B AJ27 DCR3 FPGA DM DIFFIO TX B5CF, DC7 DFoT×B73pDQ10BEDQ FFIO TX B21p, DQ DIFFIO TX B21n, DO3B DIFFIO TX B32n DO4BB RASH 0R平 DIF FIO TX B5EF, DC7B, B DM 1 DIFFIO RX B74P, DQ10B,E DQ 3 DIFFIO RX B22p. DQ3B DIFFIO TX R3p, DQ5B, B BA D7_015 IFFI RX B22n DO3B 口IFF|oTX阝33 n GND 2 DIFFIO-TX-B57F, DORB, B-DO_18 DIFFIO RX B75n,DOS10B, B OS DIFFIO RX B23 IFFlO RX B34p, DQ5B, B BA_ DIFFIO TX B57n, GND DIFFIC RX B75n. DoSn10B B Cos# 4 B58n, DQOB B cQ DIFFIO TX B76n, DQ10BB DQ 3 USB B2 CATA6 F CIFF O RX B35n, DQSn5B, B CK# B59p, DQS8B,B DQS 2 5p, DQ4B, B WE# DFFIO TX日36n DOSB BA7 O TX B6Cp, B RESET# DFR×B7D010BBDQ374C320SEz工 DIFFIO RX B26p, DO4B, BA 14 DIFFIO RX B78n, DQ10B,E DQ 36 OIFFIO RX B26n DO4BB A 15 DIFFIO RX R38n DOSR B A 5 DIFFIO RX B79p, GND D FFI TX R40p, DO5R,B 0 AJ22 DIFFIO-TX-B61p D2RE, B-0322 DIFFIO RX B79n CND D FFIO TX B40n DO58B A 1 CIFFiO TX B80p, DO10B, B DM. erc corp PART NUMBER= C7D7F3C8NES Manufacturer= Altera c HSMC LVCMOS INTERFACE PART NUMBER= 5CGXFC7D7F31C8NES 13)DR3FPG∧cKE (17)HSWA_CLK_OUT USER_ DIPSW_ FPGA[3: 0(23) (13)CDR3 FPGA_ CLK 413)DDR3 FPGA CLK 7HSVA CLK OUT NT USER_ PB FPGA[1: 0)(23) DDR3 FPGA DM3: D|(13 LVCMos only (17) HSMA CLK_IN_ P B2A》usBB2 DATA[: C(a) 3)DDR3 FPGA DM1 USER LED FPGA3: 0(9, 23) 3)DDR3 FPGA DM2 DDR3 FPGA DM DOR3_ FPGA_DQS_P[3: C](13) (17 HSMA CLK IN N S FPGA DMS USB FULL (25 DDR3 FPGA DQS N3: 01(3) USB EMPTY 125) (16, 17, 23)HSMA PRSNTn 目 》3FA0B13 DER FPGA_ A14: 0(9, 13) 3)DDR3 FPGA BAO (17)HSMA_D3: 0 IS)DDRS FPGA BA USB RDn(25) DRS FPGA BAZ CHSMA SDA L/SB WRn(25) (13)DDR3 PCIE INTERFACE Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 e Cyclone V SoC FPGA Development Kit Board NALERA Altera Corporation. All Rights Reserved 150-0321003D16X×-44184R)P1 Pate: Thursday November 21, 2013 heet Cyclone V GX Soc Bank 5 &6 CYCLONE V GX SOC BANK 6 HPS DDR, HPS A O 6: HPS DDR, HPS DM0KRH果0 IPS DDR HPS A 3 HPS DDRHPS A 4 HPS DDR, HPS A 7 CYCLONE V GX SOC BANK 5 HPS DDR, HPS A 10 HPS DDR D02 2.5 Volt R7Q_1. DIFFIO_TX_Rlp, DOIR HAG27 ENET2 TX D DDR3 HIS A HPS DDR HPS A 13 ⅨⅨⅨ DIFFIO-_TX R12 DO2R A28 HPS DDR, HPS A 15 DIFFIO TX R121L DO2R HPS DDR HFS DQ DIFFO R 2419 ENET2 TX E DIFFIO-TX_Ri4n, D02H DDR3 HPS BAO SDPC延E HPS DDR HPS DO 1 DIFFIO DIFFIO_RX R15Dz上Ac27 DDRN HIPS BAT. HPS DDR HPS BA O HPS DDR, HPS DO 14 DIFFIO 多腰 DIFFIO TK F DIFFIO RX R11p, DO2R DIFFIO TX R16D2R[As∞1ENE2ⅸcLK DIFFIO RX F11n, D02 DDR3 HPS WE 28 HPS DDR, HPS CAS# HPS GI13 PS DDR, HPS WE# ENET1 TX CLK FB(g DDR3 HPS ODT DIFFIO RX R1 H29HPS-DDRHPS-ODT-o DIFFIO RX R17n 2.50⊥t DIFFIO TX R18p, DQ3R DDR3 HPS DM2 DER HPS DM2 DIFFIO TX R180 DO3 HPS DR HPS DM 2 BarK HPS DDR HPS DM 4 Q16 S DDR HPS DQ 32 HPS DDR HFS DQ 33 RZQ 2, DIFFIO TX R24n 222 N27 HPS_DDR, HPS_0Q_21 HPS-DRRHES-DO_37IV27 DCR3 HPS DOSE HPS DDR HPS HPS DDR. HES DO HPS DDR HPS D 23 HPS DDR HFS DQ 39 PART NUMBER 5CGXFC7D7F31C8NES DDR3 HPS DM3 W30 USER DIPSW HPSO DAS NS R2H HPS DDR, HPS DM 3 HPS Gl10 23)USER DIPSW HPS(S HPS DDR, HPS DQS#f 3 H sssss 23)USER PB HFS3: C HPS DDR DDRK HPS DUST waO HPS DDR, HPS DQ 31 HPS_DDR, HPs_RESET#P30 DCR3_HPS_RESETn 4.7,17)HSMA CLK CUT P2:11 op (4, 7, 17) HSMA CLK CUT N(2: 1] FART NUMBER= 5CGXFCTD7F31C8NES (7,17) HSMA TX D_P16:0] ENET1 TX D3. 01(19) 能禁能进 DOR3 HPS RA2: . (14 (7. 17)HSMA TX D N16: 0 DDR3 HPS BAO DDRS HPS DM4.0( ( 17)HSMA_RX_P[1611 (14 DDR3 HFS BAO 5 HFS BA1 (7. 17)HSMA_ RX D_ N[160 DDR3 HPS DOS P[4.C](14) (14 DDR3 HPS CASn DDR3 HPS DCS N4: 01('4) (14 DDR3 HPS CSn Si571 VCXO ODT DDR3 HPS ODT DDR3 HPS 0Q[9: 0(14) DDR3 HPS RESETn DDR3 HPS A14. 01(14) (14)DDR3 HPS RESETn Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 e Cyclone V SoC FPGA Development Kit Board ALBRA Altera Corporation. All Rights Reserved 150-0321003D16X×-44184R)P1 Pate: Thursday November 21, 2013 heet Cyclone v GX Soc Bank 7 Micro SD/USB INTERFACE USB DATA[0] 》> USB DATA[7.01(22) R392 CYCLONE V GX SOC BANK 7 ETHERNET INTERFACE 4.70 4.70K MICTOR RSTn FNET HPS_TXD[ 0] 5∨HPs HPS nRST C ENET_HPS_TXD(3. 0)(18) JTAG HPS TDO(12) No TX UARTO TX SPIM1 SSC, HPS GPIO6 CANO RX, UARTC RX SPIM1 MISO HPS GPIO65 ENET HPS_GIX CLK(18) ENET HPS MDC (18) UARTO RX CANO TX. SPIM1-SS1. HPS-GP1062 ENET HPS RESETn(18, 21) AG HPS TDI(1 SPIMO SS0 CAN1 TX UART1 BOO CLK CSC1(10) IPS PORSEL PIMO MISO CAN1 RX UART1 CTS HPS GPI059 》 ENET HPS RXD.0(l R HPS GPIO56 HEADER 1X3-PIN HPS CLK2 UART RACE DZ SPIS1 MISO. 12C0 SCL HPS GPIO56 7、入 NET_HPS_RX CLK (18) 1100KR23 CLK HPS GPIO48 A HPS GPIO55 ENET HPS MDIC 118 38.3 3100k D1 SPISO MOSLUARTO TXHPS GPIO5. D2 SPIS0 M SO 12C1 SDA HPS GPIC51 TRACE DATA3 ENET HPS INTn i18) HPS RESETr 》 HPS RES=Tn(1021) NAND DQ6. RGMII1 RXD1,USB1 D7 HPS GP1O25 Bank 7g NAND A-E, RGMI1 TX CLK CSPI SS3, HPS GPlO14 22p AND R24 LISER LED HP5.0 S RX DV USER LED HPS(3.0(23) 1mA人R4 P3下 I NAND DO2 RGIAI NAND DO1, RGMII1 MDIC, [2C3 SDA, HPS G-1O20 QSP1_101, USB1 SIP, HPS-GPI030 FA19(210SP1 102 HEADER. 1X3-PIN HEADER. Ix3-PIN NAND RB, RGMI1 TXD3, US31 D3, HPS GP1O18 QSPI 1O3 USB1 NXT HPS GP1O32 3 D2, US31 D2, HPS OSPI SSo BOOTS 100K(1 ENE HPS TXDO F20 NAND CLE, RGMI1_TXD1, USB1 D1, HPS GFI01G SPI CLK, HPS GP1O34 R244 1.C0 NAND CE.RGM I1 TXDO. US31 0. HPS GP1O15 QSPI SS1, HPS GPI035/C19 ENET APS_INTn 3 22)SD CD D SD DAT DAT3 (22 SD DAT SDMMC D3 USB0 NXT HPS SD CMD(22) DMMC D2 USB0 DIR. HPS GPO46 nk /C (22)SD CLK SDMMC_PW/REN,USBO-D1, HPS-GPIO37/817 SD_CMD 3了 SDMMC CLK INLSBO CIK HPS GPIO44 SDMMC SD DAT1(22) BCCTSEL1 ER-LED- -FSZ 3171 SDMMC D7 USBO-D7 HPS-GPIO43 USER LED HPS3 SDMMC D5, USEC D5.HPS GP1O4 CATA6 USB DATA6 RGMIIO RXDC USE1 D4 HPS GPIO A15 USB DATA4 RGVIIO MDC, USB1 DG I2C2 SCLHPS GPIO7 USB DATA4 HEADER. 1x3-PIN 3 DATA RG|oMD| O USB′D5,2c HPS GPIOG RGMIIO TXD3 USB1 DS HPS GPIO2 s807A3 (22 USB CLK GVIIO RX CLK, USB1 CLK HPS GPIO10 USB DATA1(22) L八AR24710K RGVIIO RXD3LSB1 NXTHPS GPIO13 RGMIIO TXDC USE1 DO. HP LISB DATAO(22) (22USB NXT (22)USB DIR C15 RGVIO-RXD2, UISB1-DIR, HFS_GPIO12 RGMID_TX_CIK, HPS_ B15 R248 BOOTSEL2 RGVIIO RXD1USB1 STP HPS GPIO11 RGMIIO TX CTL HPS GPIO9 HEADER. 1*3-PIN F896 3.3V PART NUMBER 5CGXFC7D7F31C8NES ICTQS3VH257 ManufacturerIDT 2.2LF p1uF PART NUMBER =OS3VH257PAG SDA 1Q00K SV VPP (12, 16, 21 MICTOR RSTr R33 JIAG MINTOR DI (12 JTAG MICTOR TDI (12)JTAG MAICTOR TCI ITAG METOR TCK (12)JTAG MIC TOR TMS (12).ITAG-MAICTOR- TDO 19010∈ D33 2.5V REC HPS SPI SCK 11 THM. 2mm JTAG MIC SEL R1254.70K,1% SCK SCL 12C SCL HPS 10 33v Logic a=pin 10<-> pin 2(TRST from MICTOR pin 10<--> pin 9(TRST from JTAG SPI CSn 14 JTAG MIC SE MICTR TRST TAG HPS TRST GND 11D 1 CODEC SEI GND3 NC1 N4 GND5 CON Logi i=pin 6 <-> pin (Enables C244」0.1JF 0.1uF0.0u1 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 e Cyclone V SoC FPGA Development Kit Board Altera Corporation. All Rights Reserved ART NUMBERE TS5A231E 150-0321003D16X×-44184R)P1 Pate: Saturday March 28, 2015 sheet Cyclone V GX SoC Bank 8 (4, 17)HSMA D[3.C) (17)HSMA_TX D_P[16: 0 》 (17)HSMA_TX_ D_N16.0] (17)HSMA RX D_P[16: 0 (17)HSMA RX D N1E: 0 (4, 17)HSMA CLK OUT_PI2 (4, 17)HSMA CLK_OUT_ N(2: CYCLONE V GX SOC BANK 8 4, 9. 17)HSMA CLK IN P(2: 1 (4, 9, 17)HSMA CLK IN N2 HSMA TX D P15 DIFFIO TX T2p, DQ1 DIFFIO T DIFFID_RX- T23p, Do3T LF11 HSMA RX D P9 R比N DIFFIO Rx D F14DIFFIO_RX HSIA DIFFIO TX T26p, Do A91DIFFIO_RX_T7n,DQ1T DIFFIO-TX_T28p. DQ4T C3 HSI IA RX D P+ CD NT D9 DIFFIO RX T11p, D02 DIFFIO RX T2S HSMA RX D N1 DIFFIC RX T31n. DC41 HSMA TODIFFIO-RX-T13n,DQ.5n2T DIFFIO TX T32p, DC4T 成LP ASMA RX D N4 DFF。RXTD2 DIFFIO TX T34 D_PO TSWF入U DIFFIO RX T170 DIFFIO TX T18p, nQ3 -x-T35P, Dos D下 DIFFIO TX T18n0O3 DIFFIORXT37n, oS5T DIFFIO RX T19D DQ3 D FFIO R> DIFFIO TX T38n 112DIFFlO DIFFIO Tx T220. 003 R426 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 e Cyclone V SoC FPGA Development Kit Board Altera Corporation. All Rights Reserved 150-0321003D16X×-44184R)P1 Pate: Thursday November 21, 2013 heet Cyclone v GX SoC Transceivers and Power U21M Cyclone V GX SoC Transceiver 器牌器出 GXB RX L2n GXB REFCLK L2 GXE TX L2 REFCI KOl p CMU PLL(PCle (2D)SDI RX P R137 FG旧RXN33 L3p, GXB REFCLK L3p SDI RX P 0 GXB RX L4 1c上 GXB RX L4N T3 GXBTX L4N (20)SDI RX N 》 是mB3 MA RX FC(17) SMA RX NO(17) R1H 5D, GXB REFCLK L5 GXE TX L即|P3 R L511 GXB REFCLK L511 verla R137& R138 DN CLK 148 P R00∈z REFCLK1Lp SMA Connector Interface SMA Connector Interface GXE L2 1OPTION SMA XCVR RX GXE TX LGp (17, HSMA. TX P OPTION SMA XCVR TX N1 GXB RX REFCLK L7p 记 XE TX LEn xN317 GXB RX LBp, GXB REFCLK Lt XB RX LBn GXB REFCLK L8n Plaoe resislu's capacitors near SMA connector OPTION SMA XCVR RX N EF TL REFCLKZLO RREF TL Manufacturer Altera Corp FART NUMBER= 5CEXFCD7F31 CBNES CAD NoNe SDI Reference clocks Route away frm aggressor CLK148cPc64‖C.1uFc×149P 2 C SCL MAX(101修84scL CLK-I5 CLK 148 CN C65 CLK 143 SDl_CLK148UP(4)R58w 80K 》90c14N)R39~t6aKlR5 Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 e Cyclone V SoC FPGA Development Kit Board 150-0321003D16X×-44184R)P1 Pate: Thursday November 21, 2013 heet HSMA_CLK_IN_P2 R413M10) 1% HSMA_CLK_IN_N2 Cyclone V GX Soc Clocks Cyclone V GX Soc Clocks 10)CLK BOT R43~^ AF: KOn FPL BL FBD DIFFIO RXB310 Bank 3B 4, 13)DDR FPGA A[140 FPLL BL CLKOUTO, FPLL BL CLKOUTp FFLL BL FE, DIFFIO TX B37F, DCGB, B A 2 N12 DOR3-FPGA A3 USER LED FPGAT FPLL BL CLKOUT1 FPLL BL CLKOUTn DIFFIO TX B37n, Q5B BA 3 K1n DIFFIO RX B39 P USER LED FPGA3 on. DIFFIO RX R47n Bank 4A D> CLK ENEL FPGA PHY(10)- CLK2p. DIFFIO RX B47p 1C)CLK EOM FPCA CLK 50M FPGA CLKOn, DIFFIO RX B55n CLK3p, DIFFIO RX Bank 5B CLK TOP1 RX R710, DOSR F FPLL BR CLKOUTO, FPLL BR CLKOUTp, FPLL BR_ FB. DIFFIO TX R22p PCIE SMBCLK (3) 感能F多 CLK ENET FPGA P Y26 CLK ENET FPGA N Y27 CLK4p, FPLL BR FBP DI=FIO RX R23p, DO3R FPLL BR CLKOUT1, FPLL BR CLKOUTn, DIFFIO TX R22n, DQ3R D29(3) PCIE PRSNTS2×1 Bank 8A □多 HSMA CLK IN CL Kp, DIFFIO RX Tip CLKn DIFFIO RX FPLL TI CI KOUT1, FPlL TL CL KOITn, DIFFIC TX T4n, DO1T e》 HSMA CLK NO CLK6p, FPLL TL FBp, DIFF IO FPLL TL CLKCUTO PLL T- CLKOUT,FPLL TL FB. DIFFIO TX-T4U DOIT A1(iPCE PRSNT2XAD> CLKGn, FPLL TL FBn, DIFFIO rx T Alera Corp ART NUMEER= 5CGXFC7D7F31C8NES Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 e Cyclone V SoC FPGA Development Kit Board 150-0321003D16X×-44184R)P1 Pate: Thursday November 21, 2013 heet PLL 2.SV REG HPS 2.5V REG HPS 1uF 2.2uF PCIE REFCLK OLC N PCIE REFCLK SYN N DNI 0.1uF|22uF CLK DIFF1 P S570EN{12,16 VDD2 ^ VcC DanP: Consider to remove ac coupling c207 CLK DIFF1 N CSD∧MA(8,10,7 REFCLK OL2 C P C19 25.00MH7 XOUT DIFF MDRIPCIE REFCLKCLON R18入入A1001% 12C SCL MAX(8.1 8 REFCLK QL2 C N C1 .uB}R三 FCLK OL2N CLK DIFF2 P XINICLKIN DIFF2 PCIE REFCLK SYN P DanP: Consider to di1te工rnat⊥o CLK DIFF2 N PCIF REFCLK SYN N GND Programmable Oscilla:or 25V FLL 2.5VR三GHPs PART NUMBER=5152112-A1-GM2 Address 66 HEx 上上 Manufacturer = S 7427g2780 (12,16)CLK125AEN CK125A -N V REG HPS 1.0OK CLK125A EN OUT H(9)CLK ENET FPGA P U29 5(9)CLK ENET FPGA N 25 00MH7 PLL 6V REG HPS 2.5V PLL1 GND V8 PLI 1D」= VODOD 2.5 PLL1 c48 sci-8IK-且= saecs 1A) SMA input 2.5V REG HPS 2.5V CLK MUX L29 uF bluF b.1LF 51ul 》2 SCL MAX(a, D1EMSCL CLK3B I10(9)CLK BOT1 742792780 2C SDA MAX(8.10196 CLK3A luF 1uF SCA CLK2B 25Mh2 CLK2 OSC CLK SYN H Clk ino CLKIB G)CLK OSC2 y Clk in1 CLKIA CLKOB OSC1 CLK SEL 9)CLK TOP1 156 D SEL3 WAE2CLK OSC1 5V REG HP 2.5V REG HPS CMOS 65 PART NUMBER-ICS83054AGI-01 NUMBER=SI5333C-A01917-GM Manufac urer =ID OSC1 C_K SEL 1.CCK buF下1 b.1uF下1 Jse C cck Control CUI iDefau ts 25MHz 5VR三GHPs MHz 5CMHZ. 50MH 2C Address 70 HEX VCD CA CLKIN VCD 25∨REGH=s 10.0K 25.00VH VDDOO CLK5C EN (1G CLKOUT1 GND CUT CLKIN C134IENI CLKoA 22(Q)CLK ENET FPGA PHYC CLKOUT ∠sMh2 OE OSC CLK18(19Cκ DUAL FNPHY 25M止hz GND 2.5V REG HPS SL18860CC CLK2A H14 1G)CLK 100V MAX Manufac urer Silicon Labs CLK2B A13 100Mh2 PART NUMBER= SL18B3ODC _1u×8 9)CLK 100V FPGA CLK3B LUCMnz Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 GND RSVD GND e Cyclone V SoC FPGA Development Kit Board Altera Corporation. All Rights Reserved s5335 150-0321003D16X×-44184R)P1 PART NUMBER= Si5335A-B020E2-GM Pate: Thursday, November 21, 2013 heet 10 of 41

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