最新版功率因数校正（PFC）手册（下）.pdf

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PFC Handbook

http://onsemi.com

Circuit Schematics

0. 2m

2700k

PH 2

0. 2m

PH 1

D2x

1N 4007

N C P1653

Vctrl

VCC

Drv

GND

NCP1653

1N 4007

56k

1nF

470k

100 nF /

63 V

100nF

100m / 3W

2. 2k

2200k

SPP20N60

R17

PH 2

R15

R20x

10k

1N 5817

390

SPP20N60

R18

R19

10k

100m / 3W

R10

100m / 3W

RETURN

R13x

680k

R14

390k

R12

680k

R11

180k

10nF

90 to 265 Vrms

5 0 or 60 Hz line volt a ge

C13

1 mF

Type = X2

CM 2

10 A

LN Earth

C19

4. 7 nF

Type = Y2

C18

4. 7 nF

Type = Y2

C15

1mF

Type = X2

CM 1

C16

1mF

C17

1mF

R21x

680k

−

D iode bridge

RETURN

PH 1

220nF

100k

22mF

R22x

680k

R23x

680k

C14

1 mF

Type = X2

C24

220nF

C25

22mF

M C 33152

In A

GND

In B

Ou tA

Ou tB

VCC

DRV1

R13

100

C27

100pF

DRV1

VCC 2

C28

220nF

VCC 2

VCC

DRV2

RETURN

R24

2. 2k

1N 5406

Figure 7−10. Application Schematic

SPP20N60

R23

10k

R22

R28

R25

15k

CSD10060

R28

R29

15k

1N4148

CSD10060

out

R21

10k

R20

C11

330 m/450 V

C12

330 m/450 V

DRV2

DRV1

ON Semiconductor

http://onsemi.com

The performance of the board is captured in following waveforms and graphs. Figure 7−11 shows the typical waveforms

(line current, output voltage, current sense signal and rectified input voltage) for one branch at two line voltage conditions.

line

(10 A/div)

CS (negative sensing)

out

in,1

(input voltage for branch 1)

line

(10 A/div)

out

CS (negative sensing)

in,1

90 V

rms

230 V

rms

out

in,1

(input voltage for branch 1)

90 V

rms

Figure 7−11. Typical Waveforms at Low Line (Left) and High Line (Right)

Plots of Figure 7−11 portray typical waveforms at full load (I

out

= 2.1 A). “CS” is the negative voltage provided by the current

sense transformers. It is representative of the current flowing into the MOSFETs of the two branches (“CS” is the common

output of the two current sense transformers). As expected, the input voltage of the “PH1 PFC stage” (“V

in,1

”) is a rectified

sinusoid for one half-line cycle and null for the other one. The line current is properly shaped.

Figure 7−12 provides a magnified view at the top of the line sinusoid. The switching frequency is 100 kHz. The signal

“V

sense

” (identical to “CS”) is a negative representation of the MOSFET current. The current sense transformers are wired so

that only the current drawn by the MOSFET drain is monitored (possible current flowing in the opposite direction cannot be

sensed).

The waveforms are similar to those of a traditional CCM PFC.

line

(10 A/div)

sense

(negative sensing)

out

in,1

(input voltage for branch 1)

line

(10 A/div)

out

sense

(negative sensing)

in,1

90 V

rms

230 V

rms

(negative sensing)

out

90 V

rms

230 V

rms

Figure 7−12. Magnified Views of Figure 7−11 Plots

Thermal measurements

The following results were obtained using a thermal camera, after a 1/2 hour operation. The board was operating at a 25°C

ambient temperature, without fan. These data are indicative.

For the bridge, the MOSFETs and diodes, the measurements were actually made on the heat-sink as near as possible to the

components of interest.

PFC Handbook

http://onsemi.com

Measurement Conditions:

in(rms)

= 88 V I

out

= 2 A

in(avg))

= 814 W PF = 0.995

out

= 381 V THD = 9 %

Devices Bridge MOSFET1 Diode1 Coil1 MOSFET2 Diode2 Coil2 Bulk Capacitor CM EMI coil

Temperature (5C) 85 95 77 47 86 80 48 40 45

Efficiency and Total Harmonic Distortion

Figure 7−13. Efficiency Performance

OUTPUT POWER (W)

100

100 200 300 800700400 600500

EFFICIENCY (%)

230 V

rms

120 V

rms

90 V

rms

20% P

max

100 200 300 800700400 600500

900

OUTPUT POWER (W)

THD (%)

Figure 7−14. Total Harmonic Distortion Over the

Load Range

230 V

rms

120 V

rms

90 V

rms

20% P

max

Figure 7−13 portrays the efficiency over the line range, from 20% to 100% of the load.

The efficiency was measured under following conditions:

♦

The measurements were made after the board was operated at full load, low line for 30 minutes

♦ All the measurements were made consecutively without interruptions

♦

PF, THD, I

in(rms)

were measured by a power meter PM1200

♦

in(rms)

was measured directly at the input of the board by a HP 34401A multimeter

♦ V

out

was measured by a HP 34401A multimeter

♦

The input power was computed according to: P

in(avg)

+ V

in(rms)

@ I

in(rms)

@ PF

♦ Open frame, ambient temperature, no fan

Reviewing Figure 7−13, it can be noted that:

♦

Like in a conventional PFC, the efficiency is higher at high line.

♦ At low line (90 V

rms

), full load, the efficiency is in the range of 94% without a fan. When measured @ 100 V

rms

input, full load efficiency of 95% was recorded.

♦

The light load efficiency is very good. For instance, at 20% of full load, efficiency is in the range of or higher than

96%. One of the reasons for this lies in the fact that a bridgeless PFC requires relatively low Qg MOSFETs

compared to a conventional PFC for the same efficiency target at full load.

Figure 7−14 portrays the THD at 90, 120 and 230 V

rms

over the load. One can note that the total harmonic distortion remains

very low even in high line, light load (<15%) where the line current is small and more sensitive to all the sources of distortion

like the system inaccuracies and mainly the EMI filter.

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