具有恒定调谐增益和均匀子带间隔的宽带VCO，用于单芯片UHFRFID阅读器资源-CSDN文库

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一、射频识别技术概述射频识别（RFID）技术是一种无线通信技术，能够通过无线射频信号自动识别目标对象并获取相关数据，不需要人工干预。UHF射频识别（UHF RFID）是指工作在超高频段的射频识别技术，其工作频率一般在840MHz到960MHz之间，广泛应用于零售、物流和供应链管理等领域。二、PLL频率综合器在UHF RFID阅读器芯片中的应用在UHF RFID阅读器芯片中，通常使用PLL（Phase-Locked Loop）频率综合器来提供稳定和高纯度的本振信号。为了完全符合中国800/900MHz RFID草案、ISO/IEC 18000-6C协议以及ETSI 302 208-1当地法规，频率综合器的频率范围需要为840MHz到960MHz，并且在载波频率1MHz偏移处的相位噪声必须优于-126dBc/Hz。三、宽带VCO的设计要求本文介绍了一款宽带VCO的设计，该VCO用于单芯片UHF RFID阅读器。设计要求VCO在3.23GHz到4.03GHz的频率范围内工作，此范围内能够实现46.8MHz/V到50.7MHz/V的调谐增益，且变化量在±4%以内；同时，子带间隔需要维持在47MHz到49MHz之间，变化量在±2%以内；在载波频率3.6GHz处，1MHz偏移的相位噪声要达到-128.5dBc/Hz。四、宽带VCO的设计方案为了实现上述设计要求，文中提出了一种优化的计算方法以获得数字控制电容阵列单元的精确电容比。在电路实现上，采用了电阻偏置的开关电容结构，以此达到大频率范围和优化相位噪声性能。电路在0.18微米CMOS工艺中实现，整个电路消耗5.9mA的电流，供电电压为3.3V至2.5V的LDO偏置供电。五、调谐增益（KVCO）的稳定性在宽带VCO设计中，开关电容阵列（SCA）用于覆盖如此宽的频率范围并降低VCO增益（KVCO）。然而，SCA会导致KVCO的明显变化，KVCO的波动会改变环路带宽，并影响相位噪声性能和环路稳定性。为解决这一问题，文中提及了近年来提出的实现恒定环路带宽的技术方法。六、相位噪声性能的优化相位噪声性能是VCO设计中的关键指标之一。低相位噪声意味着VCO输出的信号具有更高的纯净度，这对于通信系统来说至关重要。本文介绍的VCO通过电阻偏置的开关电容结构，优化了相位噪声性能。七、CMOS工艺与电路实现电路在0.18微米CMOS工艺中实现，这表明了在较成熟的半导体制造工艺中仍可以实现高性能的射频电路设计。CMOS技术的优势包括较低的功耗、较高的集成度以及较好的可扩展性，使得它成为构建RFID阅读器等高频集成电路的理想选择。八、总结与展望本文所介绍的宽带VCO具有恒定调谐增益和均匀子带间隔，适用于单芯片UHF RFID阅读器。该VCO的设计满足了工业标准对于频率合成器的严格要求，提供了高稳定性和低相位噪声的信号输出。随着RFID技术的不断发展，类似这样高性能的集成电路设计将越来越受到重视，未来的研究与开发将会更加注重能效比和集成度的提升，以满足不断增长的市场需求。

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A Wideband VCO with Constant Tuning-Gain and

Uniform Sub-Band Interval for Single-Chip UHF RFID Reader

Jianqiao Tang, Runxi Zhang and Chunqi Shi

Institute of Microelectronic Circuits & Systems, East China Normal University, Shanghai, China

Email: rxzhang@ee.ecnu.edu.cn, cqshi@ee.ecnu.edu.cn

Abstract

A novel VCO with constant tuning-gain and uniform

sub-band interval is presented in this paper for

single-chip UHF RFID reader application. An optimized

calculation method is proposed to attain the accurate

capacitor ratio for digital-controlled capacitor array units.

The resistor-biased switched-capacitor structure is used

to achieve large frequency range and optimized phase

noise performance. The circuit is realized in 0.18μm

CMOS process and the simulation results show that the

VCO features a tuning-gain from 46.8 to 50.7MHz/V

with ±4% variation and a sub-band interval from 47 to

49 MHz with ±2% variation for frequencies from 3.23

to 4.03GHz and phase noise of -128.5dBc/Hz at 1MHz

offset from 3.6GHz carrier. The whole circuit consumes

5.9mA from a 3.3V to 2.5V LDO-biased power supply.

1. Introduction

UHF radio-frequency identification (RFID) is growing

rapidly in many areas such as retail, logistic and supply

chain management [1]. The PLL-based frequency synth-

esizer is always used to provide a stable and high-purity

LO source for UHF RFID reader chip. In order to be

fully-compliant with China 800/900MHz RFID draft [2],

ISO/IEC 18000-6C protocol [3] and ETSI 302 208-1

local regulation [4], the frequency synthesizer should

range from 840 to 960MHz with a low phase noise better

than -126dBc/Hz at 1MHz offset [5]. This value has been

deduced from various transmitter output masks. In this

paper, the voltage-controlled oscillator (VCO) operates

at four times of the carrier frequency from 3.23 to

4.03GHz. The switched-capacitor array (SCA) is used to

cover such a wideband frequency range and achieve a

relatively lower value of VCO gain (K

VCO

). However,

the SCA will cause the obvious variation of K

VCO

. The

fluctuation of K

VCO

changes loop bandwidth and

influences phase noise performance and loop stability.

Recently, several techniques have been reported to

realize a constant loop bandwidth. In [6], the open-loop

calibration technique is used to automatically adjust the

charge pump current and compensate the K

VCO

variation

which has been pre-estimated. However, because of the

PVT variation, the actual value of the fabricated K

VCO

could not be precisely forecasted. In [7], the varactor

with independent bias is used to improve the linearity of

tuning curve. But the extra noise caused by the bias

circuits will deteriorate phase noise. In addition, the

variation of the sub-band interval (f

step

) is not considered

in both of above-mentioned methods.

In this paper, a novel VCO with constant tuning-gain and

uniform sub-band interval characteristic is presented.

The digital-controlled capacitor array (DCCA) and the

digital-controlled varactor array ( D C VA) are jointly

employed to achieve a constant K

VCO

and uniform f

step

An optimized calculation method for the capacitor ratio

of DCCA units is also proposed.

÷4

Programmable

Divider

Δ∑

out

VCOLPF

AFC

PFD

ref

(24MHz)

Figure 1. Block diagram of the fractional-N PLL using

the proposed VCO

2. PLL bandwidth

To minimize phase noise variation and guarantee loop

stability, a constant loop bandwidth over the whole

output frequency range is necessary. The block diagram

of the fractional-N fourth-order type-II charge pump

PLL is shown in Fig.1 and the bandwidth of the PLL can

be written as

BW=

VCO

2πN

∙

it’s obviously that a constant K

VCO

and the stable ratio of

/N is significant to achieve an unchanged bandwidth.

If some techniques are used to keep I

/N constant, for

example, make the charge pump current match with the

variation of N [8], the bandwidth is deeply influenced by

the fluctuation of K

VCO

(1)

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具有恒定调谐增益和均匀子带间隔的宽带VCO，用于单芯片UHF RFID阅读器

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