7130 IEEE SENSORS JOURNAL, VOL. 18, NO. 17, SEPTEMBER 1, 2018
A 9.1ENOB 200MS/s Asynchronous SAR ADC
With Hybrid Single-Ended/Differential DAC
in 55-nm CMOS for Image Sensing Signals
Yuhua Liang , Member, IEEE, Ruixue Ding, and Zhangming Zhu , Member, IEEE
Abstract—A 9.1ENOB 200 MS/s asynchronous SAR analog-
to-digital converter (ADC) dealing with image sensing signals
is presented in this paper. The proposed ADC, designed
in 55-nm CMOS process technology, can work in both single-
ended and differential modes. To guarantee the ADC linearity,
a symmetrical switching method is adopted. To ensure the
reference accuracy when the ADC is in operation, a 1.2-V on-chip
quick-response LDO, which works under a 2.5-V supply, is also
integrated. To overcome the need for a clock-generation circuit
and avoid a high-speed interface circuit design, asynchronous
clock logic is chosen. In addition, the comparison cycle
is adjusted dynamically to guarantee the DAC settling
and improve the ADC throughput. In the differential
operation mode, the proposed SAR ADC exhibits a peak
signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB and a peak
spurious-free-dynamic-range (SFDR) of 68 dB with the Nyquist
input, at a 200-MS/s output rate. The ADC consumes 2.74 mW,
resulting in a figure-of-merit (FOM) of 25-fJ/conversion-step.
Meanwhile, in the single-ended mode, the SNDR and SFDR of the
ADC are 53and 64 dB, respectively. And the power consumption
is 2.25 mW, resulting in an FOM of 31-fJ/conversion-step. The
area of the proposed ADC is 280 × 380 µm
2
and the ADC core
occupies an active area of only 140 × 250 µm
2
.
Index Terms—Analog-to-digital converter, switching scheme,
successive approximation register, asynchronous, linearity.
I. INTRODUCTION
A
HIGH-PERFORMANCE analog-to-digital converters
(ADC) is always the essential building block in a CMOS
image sensor system. Taking the ultrasound imaging system
illustrated in Fig.1 for example, after the analog signals are
acquired and preprocessed by the sensing and analog front-
end blocks, the ADC is required to digitize the analog sig-
nals for subsequent processing. There are several well-known
ADC architectures to realize the analog-to-digital conversion
goal [1]–[5]. To realize the real-time high definition video
capture, most ADCs for image sensors feature a resolution
Manuscript received June 15, 2018; revised June 30, 2018; accepted
June 30, 2018. Date of publication July 13, 2018; date of current version
August 10, 2018. This work was supported in part by the National Natural
Science Foundation of China under Grant 61604111, Grant 61625403, and
Grant 61674118, in part by the China Postdoctoral Science Foundation under
Grant 2016M602772, and in part by the Fundamental Research Funds for
the Central Universities of China. The associate editor coordinating the
review of this paper and approving it for publication was Dr. Zhichao Tan.
(Corresponding author: Zhangming Zhu.)
The authors are with the Shaanxi Key Laboratory of Integrated Circuits and
Systems, School of Microelectronics, Xidian University, Xi’an 710071, China
(e-mail: zmyh@263.net).
Digital Object Identifier 10.1109/JSEN.2018.2856103
Fig. 1. The block diagram of an ultrasound sensing system.
of 8 to10 bits, and a sampling speed of tens to hundreds MS/s.
The pipeline ADC has been always the mainstream choice
in this application field [5]. Nevertheless, the realization of
a pipeline ADC has been always the mainstream choice in
this application field [5]. Nevertheless, the realization of a
pipeline ADC is proving to be more and more difficult as the
digital process is scaled down. Things are getting worse as
the power supply voltage tends to gradually decrease with the
development of the manufacturing process, which also hinder
the design of the pipeline ADC. Moreover, power efficiency
of the pipeline ADC is always so low that the die temperature
is raised, only to increase the leakage current and noise level,
and degrade image quality.
By contrast, owing to the advantages of their simple
structure and minimal usage of analog circuit, SAR
(successive approximation register) ADCs are well compatible
with the increasingly scaled-down technology and operate at
an ultra-low power supply. However, due to its successive-
approximation conversion strategy, the N-bit SAR ADC
usually requires N comparison cycles to complete one A-D
conversion. Thus, it is hard work for SAR ADCs to do
well in both throughput and resolution. Actually, since their
appearance, SAR ADCs have dominated the low-power
low-speed low/medium resolution application areas [6], [7].
In recent years, many researchers throughout the world have
devoted themselves to improving the throughput and resolution
of SAR ADCs, and several strategies have been developed.
Time interleaved ADCs are described in detail in [8]. In this
way, the overall sampling rate equals the product of the
number of channels and the sampling rate of a single channel.
Although the overall sampling rate can be improved by time
interleaving, the difficult clock and matching requirement
for different channels are always limitations for the ADC
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