From Device to System: Cross-layer Design
Exploration of Racetrack Memory
Guangyu Sun
∗
, Chao Zhang
∗
, Hehe Li
†
, Yue Zhang
§
, Weiqi Zhang
∗
, Yizi Gu
†
,
Yinan Sun
†
, J.-O. Klein
§
, D. Ravelosona
§
, Yongpan Liu
†
, Weisheng Zhao
‡§
, Huazhong Yang
†
∗
CECA, Peking University, Beijing, China
†
EE Department, Tsinghua University, Beijing, China
‡
Spintronics Interdisciplinary Center, Beihang University, Beijing, China
§
Institut d’lectronique Fondamentale, Univ. Paris-Sud/UMR 8622 CNRS, Orsay, France
Email:
∗
gsun@pku.edu.cn,
†
ypliu@tsinghua.edu.cn,
‡
weisheng.zhao@u-psud.fr
Abstract—Recently, Racetrack Memory (RM) has attracted
more and more attention of memory researchers because it has
advantages of ultra-high storage density, fast access speed, and
non-volatility. Prior research has demonstrated that RM has
potential to replace SRAM for large capacity on-chip memory
design. At the same time, it also addressed that the design space
exploration of RM could be more complicated compared to tra-
ditional on-chip memory technologies for several reasons. First,
a single RM cell introduces more device level design parameters.
Second, considering these device-level design factors, the layout
exploration of a RM array demonstrates trade-off among area,
performance, and power consumption of RM circuit level design.
Third, in the architecture level, the unique “shift” operation
results in an extra dimension for design exploration. In this paper,
we will review all these design issues in different layers and try
to reveal the relationship among them. The experimental results
demonstrate that cross-layer design exploration is necessary for
racetrack memory. In addition, a system level case study of using
RM in a sensor node is presented to demonstrate its advantages
over SRAM or STT-RAM.
I. INTRODUCTION
As the number of process elements integrated on a single
chip keeps increasing, on-chip memory design is in urgent
demand of improving storage density to cache enough data for
processing. Thus, various emerging memory technologies have
been proposed as potential candidates of replacing traditional
SRAM technology for future on-chip memory design. They
include Spin-Transfer Torque Random-Access Memory (STT-
RAM) [1], Resistive Random-Access Memory (ReRAM) [2],
Conductive Bridging Random-Access Memory (CBRAM) [3],
etc. Compared to SRAM, these emerging memory technolo-
gies have advantages of non-volatility, high storage density,
and low leakage power [1], [4].
Recently, Racetrack Memory (RM) has attracted more and
more attention of memory researchers because it can achieve
even higher storage density than the other emerging non-
volatile memory technologies (NVMs) introduced above. RM
can be considered as a new generation of spintronic based
memory technology. It can achieve ultra-high storage density
by integrating many domains in a nanowire [5]. Thus, a RM
storage cell is in the form of a tape-like structure. All these
domains in a storage cell share several access ports for read
and write operations. To this end, a domain needs to be shifted
to the position of an access port before being accessed. Though
the shift operation induces overhead of latency and energy
consumption, we can still benefit from the ultra-high storage
density of RM. This conclusion has been proved in previous
research [6], [7], [8].
Though previous research has demonstrated benefits of us-
ing RM for on-chip memory design, we believe the advantages
of RM is not full exploited. It is mainly because the design
space of a RM design is so huge that the design trade-off
must be carefully considered for different design goals. In
fact, the design space of a RM is much larger than those
of existing technologies for several reasons. First, a single
RM cell introduces more device level design parameters.
Second, considering these device-level design factors, the lay-
out exploration of a RM array demonstrates trade-off among
area, performance, and power consumption of RM circuit
level design. Third, in the architecture level, the unique shift
operation results in an extra dimension for design exploration.
In this work, we will explore the design space of a RM
design in different layers ranging from the device level to
the system level. The important design issues in different
layers are discussed and quantitatively evaluated to reflect their
impacts on design space. In addition, we try to reveal the
interaction among them and argue that a cross-layer design
exploration is critical to find a proper RM design for different
goals. The rest of this paper is organized as follows. The device
level, circuit level, and architecture level design exploration are
presented in Section II, III, and IV, respectively. In Section
V, we further provide a case study of using RM in a ultra-
low power NV-processor, followed by conclusions in the last
section.
II. D
EVICE LEVEL BASICS OF RACETRACK MEMORY
The structural concept of a racetrack memory cell is shown
in Fig. 1. It is composed of three basic parts work for
different operations. Write and read heads are used for data
input and output. Magnetic nanowires is used for data storage
and transfer [9], [10] In order to integrate with peripheral
CMOS circuits, the write and read heads are always de-
signed through magnetic tunnel junctions (MTJs). Such a
design can also help to make fast operation and low power
feasible [11]. The data transfer is based on current-induced
DW motions [12]. The mainstream controlling strategy is to
create notches or constrictions for DW pinning. The extremely
scaled distance among these artificial pinning defects can
result in considerable device storage density. In addition, three
currents, Iw, Ir and Ish, flowing in three different paths,
which are applied to perform DW nucleation, sensing, and
shifting respectively. This could improve the reliability of the
global device compared with the traditional two-terminal MTJ
structure. The first prototype fabricated in 2011 confirmed
its feasibility, although a lot of breakthroughs in terms of
material and technique remain to overcome [13]. For example,
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