A Lifetime-aware Mapping Algorithm to Extend
MTTF of Networks-on-Chip
Letian Huang
∗
, Shuyu Chen
∗
, Qiong Wu
∗
, Masoumeh Ebrahimi
†
, Junshi Wang
∗
, Shuyan Jiang
∗
, Qiang Li
∗
∗
University of Electronic Science and Technology of China, Chengdu, China, 611731
†
Royal Institute of Technology (KTH), Stockholm, Sweden
huanglt@uestc.edu.cn
Abstract—Fast aging of components has become one of the
major concerns in Systems-on-Chip with further scaling of
the submicron technology. This problem accelerates when com-
bined with improper working conditions such as unbalanced
components’ utilization. Considering the mapping algorithms
in the Networks-on-Chip domain, some routers/links might be
frequently selected for mapping while others are underutilized.
Consequently, the highly utilized components may age faster
than others which results in disconnecting the related cores
from the network. To address this issue, we propose a mapping
algorithm, called lifetime-aware neighborhood allocation (LaNA),
that takes the aging of components into account when mapping
applications. The proposed method is able to balance the wear-
out of NoC components, and thus extending the service time
of NoC. We model the lifetime as a resource consumed over
time and accordingly define the lifetime budget metric. LaNA
selects a suitable node for mapping which has the maximum
lifetime budget. Experimental results show that the lifetime-
aware mapping algorithm could improve the minimal MTTF
of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared
to NN, CoNA, WeNA and CASqA, respectively.
Keywords—many-core system; Network-on-Chip; mapping al-
gorithm; lifetime reliability
I. INTRODUCTION
Nowadays, Network-on-Chip (NoC) has been widely used
in Multi-Processor System-on-Chip (MPSoC) but the aging
issue of NoC, similar to other platforms, is emerging as a
major research concern. Escalating device defects, shrinking
feature-size and growing transistor density have negatively
impacted the reliability which can be seen in the increase of
the failure rate (both permanent and transient) [1]. Permanent
faults reduce the system lifetime [2] and therefore, techniques
are proposed to improve the systems lifetime in terms of mean
time to failure (MTTF). Currently, there are mature methods
and techniques to tolerate failures in cores due to aging. For
instance, researchers have already proposed architectures that
can gracefully tolerate up to a few hundred (>500) processor-
logic permanent faults, in a 64-node CMP [3]. Even if a
certain core is broken, it can be isolated because the core
is an independent part, then the rest of MPSoC will continue
to work. However, such well-protected components, cores, are
connected to a less-protected infrastructure, NoC. Faults in a
router can cause disabling a well-functioning core along with
the router [4]. As another consequence, the connectivity of
NoC will be devastated and the performance of MPSoC will
be severely reduced. So, enhancing the lifetime of NoC has
the same level of importance as cores in MPSoC. LaNA tries
to manage NoC reliability at run-time through task mapping
as a low overhead approach.
Mapping algorithms try to allocate applications to the cores
in an optimal way and aim to minimize the overall data
latency and/or the power dissipation of the network. Mapping
algorithms are mostly evaluated based on their defined cost
functions. An application is composed of a set of communica-
tion tasks. To map an application onto the NoC-based multi-
core system could be defined as a one-to-one mapping function
from a set of application tasks to a set of cores. Mapping
algorithms can decide the allocation of an application to the
cores based on the usage of cores and routers in the NoC-based
multi-core system.
The activity rate of one circuit is directly related to the
aging of this circuit. Since the traffic in NoC is unbalanced,
the activity of each part of a router is quite different. So, the
activity of the routers should be represented by the activity of
different paths. As shown Fig. 1, a path between the crossbars
of two routers is composed of a mux connected with output
registor, an output registor, a switch allocator for controlling
this mux and thisregister, the wires between two routers, an
input buffer, a routing computation unit and a virtual channel
allocator. For example, Fig. 1 shows the activated circuit as a
result of delivering a packet from Router A to Router B. So,
the wear condition of one path is positively correlated with
the wear condition of the wires subordinate to this path. In
this paper, we model and refer to the aging of wires which
represents the aging of paths as well.
Fig. 1. The activity of one router’s different parts are represented by the
activity of links
Most of the dynamic mapping algorithms do not consider
NoC aging, so that some wires could be aged much faster
than the others. Fig. 2(a) and (b) show a case study that
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