Intel
®
Itanium
®
Processor Family Interrupt Architecture Guide iii
Contents
1 Introduction......................................................................................................................1-1
1.1 About this Manual...............................................................................................1-1
1.2 Reference Documents........................................................................................1-1
1.3 Objectives of SAPIC...........................................................................................1-1
1.4 Terminology........................................................................................................1-2
1.4.1 Glossary ................................................................................................1-3
1.5 Revision History .................................................................................................1-5
2 SAPIC Interrupt Architecture...........................................................................................2-1
2.1 Platform Interrupt Architecture ...........................................................................2-1
2.2 Intel
®
Itanium
®
Architecture Interrupt Delivery Overview...................................2-2
2.2.1 I/O Interrupts from Remote I/O xAPIC...................................................2-2
2.2.2 Processor Local Interrupts (ITV, CMC, Performance Monitor)..............2-2
2.2.3 Interprocessor Interrupts .......................................................................2-3
2.3 Software Model ..................................................................................................2-3
2.3.1 Local SAPIC..........................................................................................2-3
2.3.2 I/O xAPIC ..............................................................................................2-6
2.3.3 Interprocessor Interrupts .....................................................................2-10
2.4 Interrupt and Processor Priorities.....................................................................2-10
2.4.1 Batch Processing of Interrupts ............................................................2-11
2.4.2 Redirectable Interrupt Delivery............................................................2-12
2.4.3 Interrupt Nesting..................................................................................2-13
2.4.4 Interrupt Masking.................................................................................2-14
2.5 Interrupt Handling.............................................................................................2-15
2.5.1 Edge-Triggered Interrupts ...................................................................2-15
2.5.2 Level-Triggered Interrupts ...................................................................2-15
2.5.3 Greater than 240 Devices ...................................................................2-18
2.5.4 NMI Handling.......................................................................................2-19
2.5.5 ExtINT Handling ..................................................................................2-19
2.5.6 Timer Interrupt Handling......................................................................2-19
2.5.7 PMI Handling.......................................................................................2-19
2.6 8259 Interrupt Controller Support (Optional)....................................................2-19
2.7 SAPIC Memory Map.........................................................................................2-20
2.7.1 Processor Interrupt Block ....................................................................2-21
2.7.2 I/O xAPIC Configuration Space...........................................................2-23
3 Platform Level Implementation........................................................................................3-1
3.1 Platform Interrupt Delivery Overview..................................................................3-1
3.2 External I/O Interrupt Delivery............................................................................3-1
3.2.1 I/O xAPIC Duties ...................................................................................3-1
3.2.2 Interrupt Transaction on the I/O Bus .....................................................3-1
3.2.3 Bridge Controller Duties ........................................................................3-2
3.2.4 Interrupt Transactions on the System Bus ............................................3-3
3.3 IPI Delivery.........................................................................................................3-3
3.4 Ordering Issues..................................................................................................3-3
3.5 Platform Topology and Routing Issues ..............................................................3-3
